Commit dd0bc75e authored by Ralf Baechle's avatar Ralf Baechle

MIPS: SB1: Remove support for Pass 1 parts.

Pass 1 parts had a number of significant erratas and were only available
in small numbers and under NDA.  Full support also required the use of a
special toolchain that kept branches properly aligned.  These workarounds
were never upstreamed and the only toolchain known to have them is
Montavista's GCC 3.0-based toolchain which completly obsoleted if not
useless these days.

So now that automated testing has tripped over the user of the
-msb1-pass1-workarounds option, rather than fixing it remove support for
pass 1 parts.

Probably nobody will notice.  I seem to own the last know pass 1 board
and I haven't noticed another one in the wild in the past decade, at
least.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4e9d324d
...@@ -2263,11 +2263,6 @@ config MIPS_CM ...@@ -2263,11 +2263,6 @@ config MIPS_CM
config MIPS_CPC config MIPS_CPC
bool bool
config SB1_PASS_1_WORKAROUNDS
bool
depends on CPU_SB1_PASS_1
default y
config SB1_PASS_2_WORKAROUNDS config SB1_PASS_2_WORKAROUNDS
bool bool
depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2) depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
......
...@@ -181,13 +181,6 @@ cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) ...@@ -181,13 +181,6 @@ cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
ifdef CONFIG_CPU_SB1
ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
KBUILD_AFLAGS_MODULE += -msb1-pass1-workarounds
KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds
endif
endif
# For smartmips configurations, there are hundreds of warnings due to ISA overrides # For smartmips configurations, there are hundreds of warnings due to ISA overrides
# in assembly and header files. smartmips is only supported for MIPS32r1 onwards # in assembly and header files. smartmips is only supported for MIPS32r1 onwards
# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or # and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
......
...@@ -13,8 +13,7 @@ ...@@ -13,8 +13,7 @@
#define R4600_V2_HIT_CACHEOP_WAR 0 #define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0 #define R5432_CP0_INTERRUPT_WAR 0
#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
extern int sb1250_m3_workaround_needed(void); extern int sb1250_m3_workaround_needed(void);
......
...@@ -81,11 +81,6 @@ choice ...@@ -81,11 +81,6 @@ choice
prompt "SiByte SOC Stepping" prompt "SiByte SOC Stepping"
depends on SIBYTE_SB1xxx_SOC depends on SIBYTE_SB1xxx_SOC
config CPU_SB1_PASS_1
bool "1250 Pass1"
depends on SIBYTE_SB1250
select CPU_HAS_PREFETCH
config CPU_SB1_PASS_2_1250 config CPU_SB1_PASS_2_1250
bool "1250 An" bool "1250 An"
depends on SIBYTE_SB1250 depends on SIBYTE_SB1250
......
...@@ -81,10 +81,7 @@ void check_bus_watcher(void) ...@@ -81,10 +81,7 @@ void check_bus_watcher(void)
{ {
u32 status, l2_err, memio_err; u32 status, l2_err, memio_err;
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS #if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
/* Destructive read, clears register and interrupt */
status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
#elif defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
/* Use non-destructive register */ /* Use non-destructive register */
status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));
#elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
......
...@@ -202,12 +202,10 @@ void __init sb1250_setup(void) ...@@ -202,12 +202,10 @@ void __init sb1250_setup(void)
switch (war_pass) { switch (war_pass) {
case K_SYS_REVISION_BCM1250_PASS1: case K_SYS_REVISION_BCM1250_PASS1:
#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, " printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
"and the kernel doesn't have the proper " "and the kernel doesn't have the proper "
"workarounds compiled in. @@@@\n"); "workarounds compiled in. @@@@\n");
bad_config = 1; bad_config = 1;
#endif
break; break;
case K_SYS_REVISION_BCM1250_PASS2: case K_SYS_REVISION_BCM1250_PASS2:
/* Pass 2 - easiest as default for now - so many numbers */ /* Pass 2 - easiest as default for now - so many numbers */
......
...@@ -1508,16 +1508,7 @@ static void sbmac_channel_start(struct sbmac_softc *s) ...@@ -1508,16 +1508,7 @@ static void sbmac_channel_start(struct sbmac_softc *s)
__raw_writeq(reg, port); __raw_writeq(reg, port);
port = s->sbm_base + R_MAC_ETHERNET_ADDR; port = s->sbm_base + R_MAC_ETHERNET_ADDR;
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
/*
* Pass1 SOCs do not receive packets addressed to the
* destination address in the R_MAC_ETHERNET_ADDR register.
* Set the value to zero.
*/
__raw_writeq(0, port);
#else
__raw_writeq(reg, port); __raw_writeq(reg, port);
#endif
/* /*
* Set the receive filter for no packets, and write values * Set the receive filter for no packets, and write values
......
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