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Commit dd15c4a0 authored by Jakub Kicinski's avatar Jakub Kicinski
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Merge branch 'r8169-improve-rtl8168g-phy-suspend-quirk' 

Heiner Kallweit says:

====================
r8169: improve RTL8168g PHY suspend quirk

According to Realtek the ERI register 0x1a8 quirk is needed to work
around a hw issue with the PHY on RTL8168g. The register needs to be
changed before powering down the PHY. Currently we don't meet this
requirement, however I'm not aware of any problems caused by this.
Therefore I see the change as an improvement.

The PHY driver has no means to access the chip ERI registers,
therefore we have to intercept MDIO writes to the BMCR register.
If the BMCR_PDOWN bit is going to be set, then let's apply the
quirk before actually powering down the PHY.
====================

Link: https://lore.kernel.org/r/9303c2cf-c521-beea-c09f-63b5dfa91b9c@gmail.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents e6e918d4 acb58657
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Showing with 90 additions and 90 deletions
drivers/net/ethernet/realtek/r8169_main.c
View file @ dd15c4a0
......@@ -746,6 +746,70 @@ static const struct rtl_cond name = { \
\
static bool name ## _check(struct rtl8169_private *tp)
static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
{
/* based on RTL8168FP_OOBMAC_BASE in vendor driver */
if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
*cmd |= 0x7f0 << 18;
}
DECLARE_RTL_COND(rtl_eriar_cond)
{
return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
}
static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
u32 val, int type)
{
u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
BUG_ON((addr & 3) || (mask == 0));
RTL_W32(tp, ERIDR, val);
r8168fp_adjust_ocp_cmd(tp, &cmd, type);
RTL_W32(tp, ERIAR, cmd);
rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
}
static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
u32 val)
{
_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
}
static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
{
u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
r8168fp_adjust_ocp_cmd(tp, &cmd, type);
RTL_W32(tp, ERIAR, cmd);
return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
RTL_R32(tp, ERIDR) : ~0;
}
static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
{
return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
}
static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
{
u32 val = rtl_eri_read(tp, addr);
rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
}
static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
{
rtl_w0w1_eri(tp, addr, p, 0);
}
static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
{
rtl_w0w1_eri(tp, addr, 0, m);
}
static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
{
if (reg & 0xffff0001) {
......@@ -808,6 +872,25 @@ static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
}
/* Work around a hw issue with RTL8168g PHY, the quirk disables
* PHY MCU interrupts before PHY power-down.
*/
static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
{
switch (tp->mac_version) {
case RTL_GIGA_MAC_VER_40:
case RTL_GIGA_MAC_VER_41:
case RTL_GIGA_MAC_VER_49:
if (value & BMCR_RESET || !(value & BMCR_PDOWN))
rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
else
rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
break;
default:
break;
}
};
static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
{
if (reg == 0x1f) {
......@@ -818,6 +901,9 @@ static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
if (tp->ocp_base != OCP_STD_PHY_BASE)
reg -= 0x10;
if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
rtl8168g_phy_suspend_quirk(tp, value);
r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
}
......@@ -1009,70 +1095,6 @@ static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
}
static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
{
/* based on RTL8168FP_OOBMAC_BASE in vendor driver */
if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
*cmd |= 0x7f0 << 18;
}
DECLARE_RTL_COND(rtl_eriar_cond)
{
return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
}
static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
u32 val, int type)
{
u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
BUG_ON((addr & 3) || (mask == 0));
RTL_W32(tp, ERIDR, val);
r8168fp_adjust_ocp_cmd(tp, &cmd, type);
RTL_W32(tp, ERIAR, cmd);
rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
}
static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
u32 val)
{
_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
}
static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
{
u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
r8168fp_adjust_ocp_cmd(tp, &cmd, type);
RTL_W32(tp, ERIAR, cmd);
return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
RTL_R32(tp, ERIDR) : ~0;
}
static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
{
return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
}
static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
{
u32 val = rtl_eri_read(tp, addr);
rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
}
static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
{
rtl_w0w1_eri(tp, addr, p, 0);
}
static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
{
rtl_w0w1_eri(tp, addr, 0, m);
}
static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
{
RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
......@@ -2210,20 +2232,8 @@ static void rtl_pll_power_down(struct rtl8169_private *tp)
case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
case RTL_GIGA_MAC_VER_37:
case RTL_GIGA_MAC_VER_39:
case RTL_GIGA_MAC_VER_43:
case RTL_GIGA_MAC_VER_44:
case RTL_GIGA_MAC_VER_45:
case RTL_GIGA_MAC_VER_46:
case RTL_GIGA_MAC_VER_47:
case RTL_GIGA_MAC_VER_48:
case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
break;
case RTL_GIGA_MAC_VER_40:
case RTL_GIGA_MAC_VER_41:
case RTL_GIGA_MAC_VER_49:
rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_41:
case RTL_GIGA_MAC_VER_43 ... RTL_GIGA_MAC_VER_63:
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
break;
default:
......@@ -2241,20 +2251,10 @@ static void rtl_pll_power_up(struct rtl8169_private *tp)
case RTL_GIGA_MAC_VER_43:
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
break;
case RTL_GIGA_MAC_VER_44:
case RTL_GIGA_MAC_VER_45:
case RTL_GIGA_MAC_VER_46:
case RTL_GIGA_MAC_VER_47:
case RTL_GIGA_MAC_VER_48:
case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_41:
case RTL_GIGA_MAC_VER_44 ... RTL_GIGA_MAC_VER_63:
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
break;
case RTL_GIGA_MAC_VER_40:
case RTL_GIGA_MAC_VER_41:
case RTL_GIGA_MAC_VER_49:
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
break;
default:
break;
}
......
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