Commit ddda8433 authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Gregory CLEMENT

arm64: dts: marvell: Add AP806-dual cache description

Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent cbafcad0
...@@ -22,6 +22,13 @@ cpu0: cpu@0 { ...@@ -22,6 +22,13 @@ cpu0: cpu@0 {
enable-method = "psci"; enable-method = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
clocks = <&cpu_clk 0>; clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
}; };
cpu1: cpu@1 { cpu1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
...@@ -30,6 +37,20 @@ cpu1: cpu@1 { ...@@ -30,6 +37,20 @@ cpu1: cpu@1 {
enable-method = "psci"; enable-method = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
clocks = <&cpu_clk 0>; clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
}; };
}; };
}; };
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