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Commit de0b9d3b authored by Florian Fainelli's avatar Florian Fainelli Committed by David S. Miller
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net: dsa: bcm_sf2: Remove duplicate code 

Now that we are using b53_common for most VLAN, FDB and bridge
operations, delete all the redundant code that we had in bcm_sf2.c to
keep only the integration specific logic that we have to deal with:
power management, link management and the external interfaces (RGMII,
MDIO).
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f458995b
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Showing with 17 additions and 950 deletions
drivers/net/dsa/bcm_sf2.c
View file @ de0b9d3b
This diff is collapsed.
drivers/net/dsa/bcm_sf2.h
View file @ de0b9d3b
...@@ -51,71 +51,9 @@ struct bcm_sf2_port_status { ...@@ -51,71 +51,9 @@ struct bcm_sf2_port_status {
struct ethtool_eee eee; struct ethtool_eee eee;
u32 vlan_ctl_mask; u16 vlan_ctl_mask;
u16 pvid;
struct net_device *bridge_dev;
};
struct bcm_sf2_arl_entry {
u8 port;
u8 mac[ETH_ALEN];
u16 vid;
u8 is_valid:1;
u8 is_age:1;
u8 is_static:1;
}; };
struct bcm_sf2_vlan {
u16 members;
u16 untag;
};
static inline void bcm_sf2_mac_from_u64(u64 src, u8 *dst)
{
unsigned int i;
for (i = 0; i < ETH_ALEN; i++)
dst[ETH_ALEN - 1 - i] = (src >> (8 * i)) & 0xff;
}
static inline u64 bcm_sf2_mac_to_u64(const u8 *src)
{
unsigned int i;
u64 dst = 0;
for (i = 0; i < ETH_ALEN; i++)
dst |= (u64)src[ETH_ALEN - 1 - i] << (8 * i);
return dst;
}
static inline void bcm_sf2_arl_to_entry(struct bcm_sf2_arl_entry *ent,
u64 mac_vid, u32 fwd_entry)
{
memset(ent, 0, sizeof(*ent));
ent->port = fwd_entry & PORTID_MASK;
ent->is_valid = !!(fwd_entry & ARL_VALID);
ent->is_age = !!(fwd_entry & ARL_AGE);
ent->is_static = !!(fwd_entry & ARL_STATIC);
bcm_sf2_mac_from_u64(mac_vid, ent->mac);
ent->vid = mac_vid >> VID_SHIFT;
}
static inline void bcm_sf2_arl_from_entry(u64 *mac_vid, u32 *fwd_entry,
const struct bcm_sf2_arl_entry *ent)
{
*mac_vid = bcm_sf2_mac_to_u64(ent->mac);
*mac_vid |= (u64)(ent->vid & VID_MASK) << VID_SHIFT;
*fwd_entry = ent->port & PORTID_MASK;
if (ent->is_valid)
*fwd_entry |= ARL_VALID;
if (ent->is_static)
*fwd_entry |= ARL_STATIC;
if (ent->is_age)
*fwd_entry |= ARL_AGE;
}
struct bcm_sf2_priv { struct bcm_sf2_priv {
/* Base registers, keep those in order with BCM_SF2_REGS_NAME */ /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
void __iomem *core; void __iomem *core;
...@@ -159,9 +97,6 @@ struct bcm_sf2_priv { ...@@ -159,9 +97,6 @@ struct bcm_sf2_priv {
struct device_node *master_mii_dn; struct device_node *master_mii_dn;
struct mii_bus *slave_mii_bus; struct mii_bus *slave_mii_bus;
struct mii_bus *master_mii_bus; struct mii_bus *master_mii_bus;
/* Cache of programmed VLANs */
struct bcm_sf2_vlan vlans[VLAN_N_VID];
}; };
static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds) static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
...@@ -171,12 +106,6 @@ static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds) ...@@ -171,12 +106,6 @@ static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
return dev->priv; return dev->priv;
} }
struct bcm_sf2_hw_stats {
const char *string;
u16 reg;
u8 sizeof_stat;
};
#define SF2_IO_MACRO(name) \ #define SF2_IO_MACRO(name) \
static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \ static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
{ \ { \
......
drivers/net/dsa/bcm_sf2_regs.h
View file @ de0b9d3b
...@@ -115,14 +115,6 @@ ...@@ -115,14 +115,6 @@
#define RX_BCST_EN (1 << 2) #define RX_BCST_EN (1 << 2)
#define RX_MCST_EN (1 << 3) #define RX_MCST_EN (1 << 3)
#define RX_UCST_EN (1 << 4) #define RX_UCST_EN (1 << 4)
#define G_MISTP_STATE_SHIFT 5
#define G_MISTP_NO_STP (0 << G_MISTP_STATE_SHIFT)
#define G_MISTP_DIS_STATE (1 << G_MISTP_STATE_SHIFT)
#define G_MISTP_BLOCK_STATE (2 << G_MISTP_STATE_SHIFT)
#define G_MISTP_LISTEN_STATE (3 << G_MISTP_STATE_SHIFT)
#define G_MISTP_LEARN_STATE (4 << G_MISTP_STATE_SHIFT)
#define G_MISTP_FWD_STATE (5 << G_MISTP_STATE_SHIFT)
#define G_MISTP_STATE_MASK 0x7
#define CORE_SWMODE 0x0002c #define CORE_SWMODE 0x0002c
#define SW_FWDG_MODE (1 << 0) #define SW_FWDG_MODE (1 << 0)
...@@ -205,75 +197,11 @@ ...@@ -205,75 +197,11 @@
#define BRCM_HDR_EN_P5 (1 << 1) #define BRCM_HDR_EN_P5 (1 << 1)
#define BRCM_HDR_EN_P7 (1 << 2) #define BRCM_HDR_EN_P7 (1 << 2)
#define CORE_BRCM_HDR_CTRL2 0x0828
#define CORE_HL_PRTC_CTRL 0x0940
#define ARP_EN (1 << 0)
#define RARP_EN (1 << 1)
#define DHCP_EN (1 << 2)
#define ICMPV4_EN (1 << 3)
#define ICMPV6_EN (1 << 4)
#define ICMPV6_FWD_MODE (1 << 5)
#define IGMP_DIP_EN (1 << 8)
#define IGMP_RPTLVE_EN (1 << 9)
#define IGMP_RTPLVE_FWD_MODE (1 << 10)
#define IGMP_QRY_EN (1 << 11)
#define IGMP_QRY_FWD_MODE (1 << 12)
#define IGMP_UKN_EN (1 << 13)
#define IGMP_UKN_FWD_MODE (1 << 14)
#define MLD_RPTDONE_EN (1 << 15)
#define MLD_RPTDONE_FWD_MODE (1 << 16)
#define MLD_QRY_EN (1 << 17)
#define MLD_QRY_FWD_MODE (1 << 18)
#define CORE_RST_MIB_CNT_EN 0x0950 #define CORE_RST_MIB_CNT_EN 0x0950
#define CORE_BRCM_HDR_RX_DIS 0x0980 #define CORE_BRCM_HDR_RX_DIS 0x0980
#define CORE_BRCM_HDR_TX_DIS 0x0988 #define CORE_BRCM_HDR_TX_DIS 0x0988
#define CORE_ARLA_NUM_ENTRIES 1024
#define CORE_ARLA_RWCTL 0x1400
#define ARL_RW (1 << 0)
#define IVL_SVL_SELECT (1 << 6)
#define ARL_STRTDN (1 << 7)
#define CORE_ARLA_MAC 0x1408
#define CORE_ARLA_VID 0x1420
#define ARLA_VIDTAB_INDX_MASK 0x1fff
#define CORE_ARLA_MACVID0 0x1440
#define MAC_MASK 0xffffffffff
#define VID_SHIFT 48
#define VID_MASK 0xfff
#define CORE_ARLA_FWD_ENTRY0 0x1460
#define PORTID_MASK 0x1ff
#define ARL_CON_SHIFT 9
#define ARL_CON_MASK 0x3
#define ARL_PRI_SHIFT 11
#define ARL_PRI_MASK 0x7
#define ARL_AGE (1 << 14)
#define ARL_STATIC (1 << 15)
#define ARL_VALID (1 << 16)
#define CORE_ARLA_MACVID_ENTRY(x) (CORE_ARLA_MACVID0 + ((x) * 0x40))
#define CORE_ARLA_FWD_ENTRY(x) (CORE_ARLA_FWD_ENTRY0 + ((x) * 0x40))
#define CORE_ARLA_SRCH_CTL 0x1540
#define ARLA_SRCH_VLID (1 << 0)
#define IVL_SVL_SELECT (1 << 6)
#define ARLA_SRCH_STDN (1 << 7)
#define CORE_ARLA_SRCH_ADR 0x1544
#define ARLA_SRCH_ADR_VALID (1 << 15)
#define CORE_ARLA_SRCH_RSLT_0_MACVID 0x1580
#define CORE_ARLA_SRCH_RSLT_0 0x15a0
#define CORE_ARLA_SRCH_RSLT_MACVID(x) (CORE_ARLA_SRCH_RSLT_0_MACVID + ((x) * 0x40))
#define CORE_ARLA_SRCH_RSLT(x) (CORE_ARLA_SRCH_RSLT_0 + ((x) * 0x40))
#define CORE_ARLA_VTBL_RWCTRL 0x1600 #define CORE_ARLA_VTBL_RWCTRL 0x1600
#define ARLA_VTBL_CMD_WRITE 0 #define ARLA_VTBL_CMD_WRITE 0
#define ARLA_VTBL_CMD_READ 1 #define ARLA_VTBL_CMD_READ 1
...@@ -297,59 +225,9 @@ ...@@ -297,59 +225,9 @@
#define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \ #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
((x) * P_TXQ_PSM_VDD_SHIFT)) ((x) * P_TXQ_PSM_VDD_SHIFT))
#define CORE_P0_MIB_OFFSET 0x8000
#define P_MIB_SIZE 0x400
#define CORE_P_MIB_OFFSET(x) (CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE)
#define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8)) #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
#define PORT_VLAN_CTRL_MASK 0x1ff #define PORT_VLAN_CTRL_MASK 0x1ff
#define CORE_VLAN_CTRL0 0xd000
#define CHANGE_1P_VID_INNER (1 << 0)
#define CHANGE_1P_VID_OUTER (1 << 1)
#define CHANGE_1Q_VID (1 << 3)
#define VLAN_LEARN_MODE_SVL (0 << 5)
#define VLAN_LEARN_MODE_IVL (3 << 5)
#define VLAN_EN (1 << 7)
#define CORE_VLAN_CTRL1 0xd004
#define EN_RSV_MCAST_FWDMAP (1 << 2)
#define EN_RSV_MCAST_UNTAG (1 << 3)
#define EN_IPMC_BYPASS_FWDMAP (1 << 5)
#define EN_IPMC_BYPASS_UNTAG (1 << 6)
#define CORE_VLAN_CTRL2 0xd008
#define EN_MIIM_BYPASS_V_FWDMAP (1 << 2)
#define EN_GMRP_GVRP_V_FWDMAP (1 << 5)
#define EN_GMRP_GVRP_UNTAG_MAP (1 << 6)
#define CORE_VLAN_CTRL3 0xd00c
#define EN_DROP_NON1Q_MASK 0x1ff
#define CORE_VLAN_CTRL4 0xd014
#define RESV_MCAST_FLOOD (1 << 1)
#define EN_DOUBLE_TAG_MASK 0x3
#define EN_DOUBLE_TAG_SHIFT 2
#define EN_MGE_REV_GMRP (1 << 4)
#define EN_MGE_REV_GVRP (1 << 5)
#define INGR_VID_CHK_SHIFT 6
#define INGR_VID_CHK_MASK 0x3
#define INGR_VID_CHK_FWD (0 << INGR_VID_CHK_SHIFT)
#define INGR_VID_CHK_DROP (1 << INGR_VID_CHK_SHIFT)
#define INGR_VID_CHK_NO_CHK (2 << INGR_VID_CHK_SHIFT)
#define INGR_VID_CHK_VID_VIOL_IMP (3 << INGR_VID_CHK_SHIFT)
#define CORE_VLAN_CTRL5 0xd018
#define EN_CPU_RX_BYP_INNER_CRCCHCK (1 << 0)
#define EN_VID_FFF_FWD (1 << 2)
#define DROP_VTABLE_MISS (1 << 3)
#define EGRESS_DIR_FRM_BYP_TRUNK_EN (1 << 4)
#define PRESV_NON1Q (1 << 6)
#define CORE_VLAN_CTRL6 0xd01c
#define STRICT_SFD_DETECT (1 << 0)
#define DIS_ARL_BUST_LMIT (1 << 4)
#define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8)) #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
#define CFI_SHIFT 12 #define CFI_SHIFT 12
#define PRI_SHIFT 13 #define PRI_SHIFT 13
......
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