Commit df0835a8 authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown

ASoC: dt-bindings: fsl_spdif: Add two PLL clock source

Add two PLL clock source, they are the parent clocks of root clock
one is for 8kHz series rates, another one is for 11kHz series rates.
They are optional clocks, if there are such clocks, then driver
can switch between them for supporting more accurate rates.
Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1656667961-1799-6-git-send-email-shengjiu.wang@nxp.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7cb7f07d
...@@ -58,6 +58,8 @@ properties: ...@@ -58,6 +58,8 @@ properties:
slave of the Shared Peripheral Bus and when two or more bus masters slave of the Shared Peripheral Bus and when two or more bus masters
(CPU, DMA or DSP) try to access it. This property is optional depending (CPU, DMA or DSP) try to access it. This property is optional depending
on the SoC design. on the SoC design.
- description: PLL clock source for 8kHz series rate, optional.
- description: PLL clock source for 11khz series rate, optional.
minItems: 9 minItems: 9
clock-names: clock-names:
...@@ -72,6 +74,8 @@ properties: ...@@ -72,6 +74,8 @@ properties:
- const: rxtx6 - const: rxtx6
- const: rxtx7 - const: rxtx7
- const: spba - const: spba
- const: pll8k
- const: pll11k
minItems: 9 minItems: 9
big-endian: big-endian:
......
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