Commit dfcca60b authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville

ath9k_hw: Fix MCI init for AGC calibration

When AGC calibration is to be done, a GPM message with the
payload, MCI_GPM_WLAN_CAL_REQ has to be sent. Currently this falls
within the IQ-CAL code block which is incorrect. Fix this by using
a separate variable to decide when IQ-CAL is to be done separately
and call ar9003_mci_init_cal_req correctly.
Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 4656b8f6
...@@ -967,7 +967,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, ...@@ -967,7 +967,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
struct ath9k_hw_cal_data *caldata = ah->caldata; struct ath9k_hw_cal_data *caldata = ah->caldata;
bool txiqcal_done = false, txclcal_done = false; bool txiqcal_done = false, txclcal_done = false;
bool is_reusable = true, status = true; bool is_reusable = true, status = true;
bool run_rtt_cal = false, run_agc_cal; bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT); bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL | u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
AR_PHY_AGC_CONTROL_FLTR_CAL | AR_PHY_AGC_CONTROL_FLTR_CAL |
...@@ -1034,19 +1034,22 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, ...@@ -1034,19 +1034,22 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL); AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
txiqcal_done = run_agc_cal = true; txiqcal_done = run_agc_cal = true;
goto skip_tx_iqcal; } else if (caldata && !caldata->done_txiqcal_once) {
} else if (caldata && !caldata->done_txiqcal_once)
run_agc_cal = true; run_agc_cal = true;
sep_iq_cal = true;
}
skip_tx_iqcal:
if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal) if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
ar9003_mci_init_cal_req(ah, &is_reusable); ar9003_mci_init_cal_req(ah, &is_reusable);
if (sep_iq_cal) {
txiqcal_done = ar9003_hw_tx_iq_cal_run(ah); txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
udelay(5); udelay(5);
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
}
skip_tx_iqcal:
if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) { if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
/* Calibrate the AGC */ /* Calibrate the AGC */
REG_WRITE(ah, AR_PHY_AGC_CONTROL, REG_WRITE(ah, AR_PHY_AGC_CONTROL,
......
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