Commit dfe58f20 authored by Ben Zhang's avatar Ben Zhang Committed by Mark Brown

ASoC: rt5677: keep analog power register at SND_SOC_BIAS_OFF

Instead of clearing RT5677_PWR_ANLG2 (MX-64h) to 0 at SND_SOC_BIAS_OFF,
we only clear the RT5677_PWR_CORE bit which is set at SND_SOC_BIAS_PREPARE.
MICBIAS control bits are left unchanged.

This fixed the bug where if MICBIAS1 widget is forced on, MICBIAS
control bits will be cleared at suspend and never turned back on again,
since DAPM thinks the widget is always on.
Signed-off-by: default avatarBen Zhang <benzh@chromium.org>
Signed-off-by: default avatarCurtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20190906194636.217881-3-cujomalainey@chromium.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 33b773dc
...@@ -4493,11 +4493,11 @@ static int rt5677_set_bias_level(struct snd_soc_component *component, ...@@ -4493,11 +4493,11 @@ static int rt5677_set_bias_level(struct snd_soc_component *component,
case SND_SOC_BIAS_OFF: case SND_SOC_BIAS_OFF:
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
2 << RT5677_LDO1_SEL_SFT | 2 << RT5677_LDO1_SEL_SFT |
2 << RT5677_LDO2_SEL_SFT); 2 << RT5677_LDO2_SEL_SFT);
regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CORE, 0);
regmap_update_bits(rt5677->regmap, regmap_update_bits(rt5677->regmap,
RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
......
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