Commit e03ac9f0 authored by Nikolay Martynov's avatar Nikolay Martynov Committed by Ralf Baechle

mips: Fix CPC_BASE_ADDR mask to match datasheet

According to 'MIPS32® interAptivTM Multiprocessing
System Programmer’s Guide' CPC_BASE_ADDR takes bits [31:15].

This change is tested ith mt7621 which wasn't working without it.
Signed-off-by: default avatarNikolay Martynov <mar.kolya@gmail.com>
Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11766/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 44549e8f
...@@ -290,8 +290,8 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) ...@@ -290,8 +290,8 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
#define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0)
/* GCR_CPC_BASE register fields */ /* GCR_CPC_BASE register fields */
#define CM_GCR_CPC_BASE_CPCBASE_SHF 17 #define CM_GCR_CPC_BASE_CPCBASE_SHF 15
#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) #define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x1ffff) << 15)
#define CM_GCR_CPC_BASE_CPCEN_SHF 0 #define CM_GCR_CPC_BASE_CPCEN_SHF 0
#define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0)
......
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