Commit e26b3006 authored by Eugen Hristev's avatar Eugen Hristev Committed by Stephen Boyd

clk: at91: clk-master: add 5th divisor for mck master

clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.
Reported-by: default avatarMihai Sain <mihai.sain@microchip.com>
Signed-off-by: default avatarEugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 83d00287
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
#define MASTER_PRES_MASK 0x7 #define MASTER_PRES_MASK 0x7
#define MASTER_PRES_MAX MASTER_PRES_MASK #define MASTER_PRES_MAX MASTER_PRES_MASK
#define MASTER_DIV_SHIFT 8 #define MASTER_DIV_SHIFT 8
#define MASTER_DIV_MASK 0x3 #define MASTER_DIV_MASK 0x7
#define PMC_MCR 0x30 #define PMC_MCR 0x30
#define PMC_MCR_ID_MSK GENMASK(3, 0) #define PMC_MCR_ID_MSK GENMASK(3, 0)
......
...@@ -48,7 +48,7 @@ extern const struct clk_master_layout at91sam9x5_master_layout; ...@@ -48,7 +48,7 @@ extern const struct clk_master_layout at91sam9x5_master_layout;
struct clk_master_characteristics { struct clk_master_characteristics {
struct clk_range output; struct clk_range output;
u32 divisors[4]; u32 divisors[5];
u8 have_div3_pres; u8 have_div3_pres;
}; };
......
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