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Commit e26ccc46 authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
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can: at91_can: use a consistent indention 

Convert the driver to use a consistent indention of one space after
defines and in enums. That makes it easier to add new defines, which
will be done in the coming patches.

Link: https://lore.kernel.org/all/20231005-at91_can-rx_offload-v2-2-9987d53600e0@pengutronix.deSigned-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 9beebc2b
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Showing with 64 additions and 64 deletions
drivers/net/can/at91_can.c
View file @ e26ccc46
...@@ -25,89 +25,89 @@ ...@@ -25,89 +25,89 @@
#include <linux/can/dev.h> #include <linux/can/dev.h>
#include <linux/can/error.h> #include <linux/can/error.h>
#define AT91_MB_MASK(i) ((1 << (i)) - 1) #define AT91_MB_MASK(i) ((1 << (i)) - 1)
/* Common registers */ /* Common registers */
enum at91_reg { enum at91_reg {
AT91_MR = 0x000, AT91_MR = 0x000,
AT91_IER = 0x004, AT91_IER = 0x004,
AT91_IDR = 0x008, AT91_IDR = 0x008,
AT91_IMR = 0x00C, AT91_IMR = 0x00C,
AT91_SR = 0x010, AT91_SR = 0x010,
AT91_BR = 0x014, AT91_BR = 0x014,
AT91_TIM = 0x018, AT91_TIM = 0x018,
AT91_TIMESTP = 0x01C, AT91_TIMESTP = 0x01C,
AT91_ECR = 0x020, AT91_ECR = 0x020,
AT91_TCR = 0x024, AT91_TCR = 0x024,
AT91_ACR = 0x028, AT91_ACR = 0x028,
}; };
/* Mailbox registers (0 <= i <= 15) */ /* Mailbox registers (0 <= i <= 15) */
#define AT91_MMR(i) ((enum at91_reg)(0x200 + ((i) * 0x20))) #define AT91_MMR(i) ((enum at91_reg)(0x200 + ((i) * 0x20)))
#define AT91_MAM(i) ((enum at91_reg)(0x204 + ((i) * 0x20))) #define AT91_MAM(i) ((enum at91_reg)(0x204 + ((i) * 0x20)))
#define AT91_MID(i) ((enum at91_reg)(0x208 + ((i) * 0x20))) #define AT91_MID(i) ((enum at91_reg)(0x208 + ((i) * 0x20)))
#define AT91_MFID(i) ((enum at91_reg)(0x20C + ((i) * 0x20))) #define AT91_MFID(i) ((enum at91_reg)(0x20C + ((i) * 0x20)))
#define AT91_MSR(i) ((enum at91_reg)(0x210 + ((i) * 0x20))) #define AT91_MSR(i) ((enum at91_reg)(0x210 + ((i) * 0x20)))
#define AT91_MDL(i) ((enum at91_reg)(0x214 + ((i) * 0x20))) #define AT91_MDL(i) ((enum at91_reg)(0x214 + ((i) * 0x20)))
#define AT91_MDH(i) ((enum at91_reg)(0x218 + ((i) * 0x20))) #define AT91_MDH(i) ((enum at91_reg)(0x218 + ((i) * 0x20)))
#define AT91_MCR(i) ((enum at91_reg)(0x21C + ((i) * 0x20))) #define AT91_MCR(i) ((enum at91_reg)(0x21C + ((i) * 0x20)))
/* Register bits */ /* Register bits */
#define AT91_MR_CANEN BIT(0) #define AT91_MR_CANEN BIT(0)
#define AT91_MR_LPM BIT(1) #define AT91_MR_LPM BIT(1)
#define AT91_MR_ABM BIT(2) #define AT91_MR_ABM BIT(2)
#define AT91_MR_OVL BIT(3) #define AT91_MR_OVL BIT(3)
#define AT91_MR_TEOF BIT(4) #define AT91_MR_TEOF BIT(4)
#define AT91_MR_TTM BIT(5) #define AT91_MR_TTM BIT(5)
#define AT91_MR_TIMFRZ BIT(6) #define AT91_MR_TIMFRZ BIT(6)
#define AT91_MR_DRPT BIT(7) #define AT91_MR_DRPT BIT(7)
#define AT91_SR_RBSY BIT(29) #define AT91_SR_RBSY BIT(29)
#define AT91_MMR_PRIO_SHIFT (16) #define AT91_MMR_PRIO_SHIFT (16)
#define AT91_MID_MIDE BIT(29) #define AT91_MID_MIDE BIT(29)
#define AT91_MSR_MRTR BIT(20) #define AT91_MSR_MRTR BIT(20)
#define AT91_MSR_MABT BIT(22) #define AT91_MSR_MABT BIT(22)
#define AT91_MSR_MRDY BIT(23) #define AT91_MSR_MRDY BIT(23)
#define AT91_MSR_MMI BIT(24) #define AT91_MSR_MMI BIT(24)
#define AT91_MCR_MRTR BIT(20) #define AT91_MCR_MRTR BIT(20)
#define AT91_MCR_MTCR BIT(23) #define AT91_MCR_MTCR BIT(23)
/* Mailbox Modes */ /* Mailbox Modes */
enum at91_mb_mode { enum at91_mb_mode {
AT91_MB_MODE_DISABLED = 0, AT91_MB_MODE_DISABLED = 0,
AT91_MB_MODE_RX = 1, AT91_MB_MODE_RX = 1,
AT91_MB_MODE_RX_OVRWR = 2, AT91_MB_MODE_RX_OVRWR = 2,
AT91_MB_MODE_TX = 3, AT91_MB_MODE_TX = 3,
AT91_MB_MODE_CONSUMER = 4, AT91_MB_MODE_CONSUMER = 4,
AT91_MB_MODE_PRODUCER = 5, AT91_MB_MODE_PRODUCER = 5,
}; };
/* Interrupt mask bits */ /* Interrupt mask bits */
#define AT91_IRQ_ERRA BIT(16) #define AT91_IRQ_ERRA BIT(16)
#define AT91_IRQ_WARN BIT(17) #define AT91_IRQ_WARN BIT(17)
#define AT91_IRQ_ERRP BIT(18) #define AT91_IRQ_ERRP BIT(18)
#define AT91_IRQ_BOFF BIT(19) #define AT91_IRQ_BOFF BIT(19)
#define AT91_IRQ_SLEEP BIT(20) #define AT91_IRQ_SLEEP BIT(20)
#define AT91_IRQ_WAKEUP BIT(21) #define AT91_IRQ_WAKEUP BIT(21)
#define AT91_IRQ_TOVF BIT(22) #define AT91_IRQ_TOVF BIT(22)
#define AT91_IRQ_TSTP BIT(23) #define AT91_IRQ_TSTP BIT(23)
#define AT91_IRQ_CERR BIT(24) #define AT91_IRQ_CERR BIT(24)
#define AT91_IRQ_SERR BIT(25) #define AT91_IRQ_SERR BIT(25)
#define AT91_IRQ_AERR BIT(26) #define AT91_IRQ_AERR BIT(26)
#define AT91_IRQ_FERR BIT(27) #define AT91_IRQ_FERR BIT(27)
#define AT91_IRQ_BERR BIT(28) #define AT91_IRQ_BERR BIT(28)
#define AT91_IRQ_ERR_ALL (0x1fff0000) #define AT91_IRQ_ERR_ALL (0x1fff0000)
#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
AT91_IRQ_ERRP | AT91_IRQ_BOFF) AT91_IRQ_ERRP | AT91_IRQ_BOFF)
#define AT91_IRQ_ALL (0x1fffffff) #define AT91_IRQ_ALL (0x1fffffff)
enum at91_devtype { enum at91_devtype {
AT91_DEVTYPE_SAM9263, AT91_DEVTYPE_SAM9263,
......
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