Commit e343d34a authored by Jack Yu's avatar Jack Yu Committed by Mark Brown

ASoC: rt715-sdca: fix clock stop prepare timeout issue

Fix clock stop prepare timeout issue (#2853).
The trigger of internal circuit which belong to
“SDCA preset stuffs” was not set correctly in previous driver,
which could block clock_stop_preparation state.
Add the correct register setting to fix it.

Fixes: 20d17057 ('ASoC: rt715-sdca: Add RT715 sdca vendor-specific driver')
Signed-off-by: default avatarJack Yu <jack.yu@realtek.com>
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20210607222239.582139-12-pierre-louis.bossart@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent dbc07517
...@@ -70,6 +70,7 @@ static bool rt715_sdca_mbq_readable_register(struct device *dev, unsigned int re ...@@ -70,6 +70,7 @@ static bool rt715_sdca_mbq_readable_register(struct device *dev, unsigned int re
case 0x2000036: case 0x2000036:
case 0x2000037: case 0x2000037:
case 0x2000039: case 0x2000039:
case 0x2000044:
case 0x6100000: case 0x6100000:
return true; return true;
default: default:
......
...@@ -113,6 +113,7 @@ static const struct reg_default rt715_mbq_reg_defaults_sdca[] = { ...@@ -113,6 +113,7 @@ static const struct reg_default rt715_mbq_reg_defaults_sdca[] = {
{ 0x2000036, 0x0000 }, { 0x2000036, 0x0000 },
{ 0x2000037, 0x0000 }, { 0x2000037, 0x0000 },
{ 0x2000039, 0xaa81 }, { 0x2000039, 0xaa81 },
{ 0x2000044, 0x0202 },
{ 0x6100000, 0x0100 }, { 0x6100000, 0x0100 },
{ SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC8_9_VOL, { SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_FU_ADC8_9_VOL,
RT715_SDCA_FU_VOL_CTRL, CH_01), 0x00 }, RT715_SDCA_FU_VOL_CTRL, CH_01), 0x00 },
......
...@@ -1054,6 +1054,9 @@ int rt715_sdca_io_init(struct device *dev, struct sdw_slave *slave) ...@@ -1054,6 +1054,9 @@ int rt715_sdca_io_init(struct device *dev, struct sdw_slave *slave)
rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG, rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
RT715_REV_1, 0x40, 0x40); RT715_REV_1, 0x40, 0x40);
} }
/* DFLL Calibration trigger */
rt715_sdca_index_update_bits(rt715, RT715_VENDOR_REG,
RT715_DFLL_VAD, 0x1, 0x1);
/* trigger mode = VAD enable */ /* trigger mode = VAD enable */
regmap_write(rt715->regmap, regmap_write(rt715->regmap,
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN, SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
......
...@@ -81,6 +81,7 @@ struct rt715_sdca_kcontrol_private { ...@@ -81,6 +81,7 @@ struct rt715_sdca_kcontrol_private {
#define RT715_AD_FUNC_EN 0x36 #define RT715_AD_FUNC_EN 0x36
#define RT715_REV_1 0x37 #define RT715_REV_1 0x37
#define RT715_SDW_INPUT_SEL 0x39 #define RT715_SDW_INPUT_SEL 0x39
#define RT715_DFLL_VAD 0x44
#define RT715_EXT_DMIC_CLK_CTRL2 0x54 #define RT715_EXT_DMIC_CLK_CTRL2 0x54
/* Index (NID:61h) */ /* Index (NID:61h) */
......
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