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Commit e42780b6 authored by Dmitry Kravkov's avatar Dmitry Kravkov Committed by David S. Miller
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bnx2x: Utilize FW 7.10.51 

 - (L2) In some multi-function configurations, inter-PF and inter-VF
   Tx switching is incorrectly enabled.

 - (L2) Wrong assert code in FLR final cleanup in case it is sent not
   after FLR.

 - (L2) Chip may stall in very rare cases under heavy traffic with FW GRO
   enabled.

 - (L2) VF malicious notification error fixes.

 - (L2) Default gre tunnel to IPGRE which allows proper RSS for IPGRE packets,
   L2GRE traffic will reach single queue.

 - (FCoE) Fix data being placed in wrong buffer when corrupt FCoE frame is
   received.

 - (FCoE) Burst of FIP packets with destination MAC of ALL-FCF_MACs
   causes FCoE traffic to stop.
Signed-off-by: default avatarDmitry Kravkov <Dmitry.Kravkov@qlogic.com>
Signed-off-by: default avatarYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: default avatarAriel Elior <Ariel.Elior@qlogic.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c0b80236
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Showing with 345 additions and 224 deletions
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
View file @ e42780b6
...@@ -2082,6 +2082,10 @@ int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, ...@@ -2082,6 +2082,10 @@ int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
__set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags); __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
if (rss_obj->udp_rss_v6) if (rss_obj->udp_rss_v6)
__set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags); __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
if (!CHIP_IS_E1x(bp))
/* valid only for TUNN_MODE_GRE tunnel mode */
__set_bit(BNX2X_RSS_GRE_INNER_HDRS, &params.rss_flags);
} else { } else {
__set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags); __set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags);
} }
...@@ -3441,26 +3445,6 @@ static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb, ...@@ -3441,26 +3445,6 @@ static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
} }
#endif #endif
static void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data,
u32 xmit_type)
{
struct ipv6hdr *ipv6;
*parsing_data |= (skb_shinfo(skb)->gso_size <<
ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
ETH_TX_PARSE_BD_E2_LSO_MSS;
if (xmit_type & XMIT_GSO_ENC_V6)
ipv6 = inner_ipv6_hdr(skb);
else if (xmit_type & XMIT_GSO_V6)
ipv6 = ipv6_hdr(skb);
else
ipv6 = NULL;
if (ipv6 && ipv6->nexthdr == NEXTHDR_IPV6)
*parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
}
/** /**
* bnx2x_set_pbd_gso - update PBD in GSO case. * bnx2x_set_pbd_gso - update PBD in GSO case.
* *
...@@ -3470,7 +3454,6 @@ static void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data, ...@@ -3470,7 +3454,6 @@ static void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data,
*/ */
static void bnx2x_set_pbd_gso(struct sk_buff *skb, static void bnx2x_set_pbd_gso(struct sk_buff *skb,
struct eth_tx_parse_bd_e1x *pbd, struct eth_tx_parse_bd_e1x *pbd,
struct eth_tx_start_bd *tx_start_bd,
u32 xmit_type) u32 xmit_type)
{ {
pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size); pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
...@@ -3483,9 +3466,6 @@ static void bnx2x_set_pbd_gso(struct sk_buff *skb, ...@@ -3483,9 +3466,6 @@ static void bnx2x_set_pbd_gso(struct sk_buff *skb,
bswab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr, bswab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
ip_hdr(skb)->daddr, ip_hdr(skb)->daddr,
0, IPPROTO_TCP, 0)); 0, IPPROTO_TCP, 0));
/* GSO on 57710/57711 needs FW to calculate IP checksum */
tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
} else { } else {
pbd->tcp_pseudo_csum = pbd->tcp_pseudo_csum =
bswab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, bswab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
...@@ -3657,18 +3637,23 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb, ...@@ -3657,18 +3637,23 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
(__force u32)iph->tot_len - (__force u32)iph->tot_len -
(__force u32)iph->frag_off; (__force u32)iph->frag_off;
outerip_len = iph->ihl << 1;
pbd2->fw_ip_csum_wo_len_flags_frag = pbd2->fw_ip_csum_wo_len_flags_frag =
bswab16(csum_fold((__force __wsum)csum)); bswab16(csum_fold((__force __wsum)csum));
} else { } else {
pbd2->fw_ip_hdr_to_payload_w = pbd2->fw_ip_hdr_to_payload_w =
hlen_w - ((sizeof(struct ipv6hdr)) >> 1); hlen_w - ((sizeof(struct ipv6hdr)) >> 1);
pbd_e2->data.tunnel_data.flags |=
1 /*IPv6*/ << ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER;
} }
pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq); pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq);
pbd2->tcp_flags = pbd_tcp_flags(inner_tcp_hdr(skb)); pbd2->tcp_flags = pbd_tcp_flags(inner_tcp_hdr(skb));
if (xmit_type & XMIT_GSO_V4) { /* inner IP header info */
if (xmit_type & XMIT_CSUM_ENC_V4) {
pbd2->hw_ip_id = bswab16(inner_ip_hdr(skb)->id); pbd2->hw_ip_id = bswab16(inner_ip_hdr(skb)->id);
pbd_e2->data.tunnel_data.pseudo_csum = pbd_e2->data.tunnel_data.pseudo_csum =
...@@ -3676,8 +3661,6 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb, ...@@ -3676,8 +3661,6 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
inner_ip_hdr(skb)->saddr, inner_ip_hdr(skb)->saddr,
inner_ip_hdr(skb)->daddr, inner_ip_hdr(skb)->daddr,
0, IPPROTO_TCP, 0)); 0, IPPROTO_TCP, 0));
outerip_len = ip_hdr(skb)->ihl << 1;
} else { } else {
pbd_e2->data.tunnel_data.pseudo_csum = pbd_e2->data.tunnel_data.pseudo_csum =
bswab16(~csum_ipv6_magic( bswab16(~csum_ipv6_magic(
...@@ -3690,8 +3673,6 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb, ...@@ -3690,8 +3673,6 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
*global_data |= *global_data |=
outerip_off | outerip_off |
(!!(xmit_type & XMIT_CSUM_V6) <<
ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT) |
(outerip_len << (outerip_len <<
ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT) | ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT) |
((skb->protocol == cpu_to_be16(ETH_P_8021Q)) << ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
...@@ -3703,6 +3684,23 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb, ...@@ -3703,6 +3684,23 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
} }
} }
static inline void bnx2x_set_ipv6_ext_e2(struct sk_buff *skb, u32 *parsing_data,
u32 xmit_type)
{
struct ipv6hdr *ipv6;
if (!(xmit_type & (XMIT_GSO_ENC_V6 | XMIT_GSO_V6)))
return;
if (xmit_type & XMIT_GSO_ENC_V6)
ipv6 = inner_ipv6_hdr(skb);
else /* XMIT_GSO_V6 */
ipv6 = ipv6_hdr(skb);
if (ipv6->nexthdr == NEXTHDR_IPV6)
*parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
}
/* called with netif_tx_lock /* called with netif_tx_lock
* bnx2x_tx_int() runs without netif_tx_lock unless it needs to call * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
* netif_wake_queue() * netif_wake_queue()
...@@ -3919,6 +3917,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) ...@@ -3919,6 +3917,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
xmit_type); xmit_type);
} }
bnx2x_set_ipv6_ext_e2(skb, &pbd_e2_parsing_data, xmit_type);
/* Add the macs to the parsing BD if this is a vf or if /* Add the macs to the parsing BD if this is a vf or if
* Tx Switching is enabled. * Tx Switching is enabled.
*/ */
...@@ -3984,10 +3983,12 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) ...@@ -3984,10 +3983,12 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
bd_prod); bd_prod);
} }
if (!CHIP_IS_E1x(bp)) if (!CHIP_IS_E1x(bp))
bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data, pbd_e2_parsing_data |=
xmit_type); (skb_shinfo(skb)->gso_size <<
ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
ETH_TX_PARSE_BD_E2_LSO_MSS;
else else
bnx2x_set_pbd_gso(skb, pbd_e1x, first_bd, xmit_type); bnx2x_set_pbd_gso(skb, pbd_e1x, xmit_type);
} }
/* Set the PBD's parsing_data field if not zero /* Set the PBD's parsing_data field if not zero
......
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
View file @ e42780b6
...@@ -932,8 +932,9 @@ static inline int bnx2x_func_start(struct bnx2x *bp) ...@@ -932,8 +932,9 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
else /* CHIP_IS_E1X */ else /* CHIP_IS_E1X */
start_params->network_cos_mode = FW_WRR; start_params->network_cos_mode = FW_WRR;
start_params->gre_tunnel_mode = L2GRE_TUNNEL; start_params->tunnel_mode = TUNN_MODE_GRE;
start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; start_params->gre_tunnel_type = IPGRE_TUNNEL;
start_params->inner_gre_rss_en = 1;
return bnx2x_func_state_change(bp, &func_params); return bnx2x_func_state_change(bp, &func_params);
} }
......
drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
View file @ e42780b6
...@@ -10,170 +10,170 @@ ...@@ -10,170 +10,170 @@
#ifndef BNX2X_FW_DEFS_H #ifndef BNX2X_FW_DEFS_H
#define BNX2X_FW_DEFS_H #define BNX2X_FW_DEFS_H
#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base) #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[147].base + ((assertListEntry) * IRO[147].m1)) (IRO[151].base + ((assertListEntry) * IRO[151].m1))
#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \ #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
(IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \ (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
IRO[153].m2)) IRO[157].m2))
#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \ #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
(IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \ (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
IRO[154].m2)) IRO[158].m2))
#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \ #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
(IRO[159].base + ((funcId) * IRO[159].m1)) (IRO[163].base + ((funcId) * IRO[163].m1))
#define CSTORM_FUNC_EN_OFFSET(funcId) \ #define CSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[149].base + ((funcId) * IRO[149].m1)) (IRO[153].base + ((funcId) * IRO[153].m1))
#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \ #define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
(IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2)) (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \ #define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
(IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \ (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
* IRO[138].m2) + ((sbId) * IRO[138].m3)) * IRO[142].m2) + ((sbId) * IRO[142].m3))
#define CSTORM_IGU_MODE_OFFSET (IRO[157].base) #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
(IRO[317].base + ((pfId) * IRO[317].m1)) (IRO[323].base + ((pfId) * IRO[323].m1))
#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
(IRO[318].base + ((pfId) * IRO[318].m1)) (IRO[324].base + ((pfId) * IRO[324].m1))
#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
(IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2)) (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
(IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2)) (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
(IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2)) (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
(IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2)) (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
(IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
(IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2)) (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
(IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
(IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2)) (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
(IRO[316].base + ((pfId) * IRO[316].m1)) (IRO[322].base + ((pfId) * IRO[322].m1))
#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
(IRO[308].base + ((pfId) * IRO[308].m1)) (IRO[314].base + ((pfId) * IRO[314].m1))
#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
(IRO[307].base + ((pfId) * IRO[307].m1)) (IRO[313].base + ((pfId) * IRO[313].m1))
#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
(IRO[306].base + ((pfId) * IRO[306].m1)) (IRO[312].base + ((pfId) * IRO[312].m1))
#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
(IRO[151].base + ((funcId) * IRO[151].m1)) (IRO[155].base + ((funcId) * IRO[155].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
(IRO[142].base + ((pfId) * IRO[142].m1)) (IRO[146].base + ((pfId) * IRO[146].m1))
#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \ #define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
(IRO[143].base + ((pfId) * IRO[143].m1)) (IRO[147].base + ((pfId) * IRO[147].m1))
#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \ #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
(IRO[141].base + ((pfId) * IRO[141].m1)) (IRO[145].base + ((pfId) * IRO[145].m1))
#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size) #define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \ #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
(IRO[144].base + ((pfId) * IRO[144].m1)) (IRO[148].base + ((pfId) * IRO[148].m1))
#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size) #define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \ #define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
(IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2)) (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \ #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
(IRO[133].base + ((sbId) * IRO[133].m1)) (IRO[137].base + ((sbId) * IRO[137].m1))
#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \ #define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
(IRO[134].base + ((sbId) * IRO[134].m1)) (IRO[138].base + ((sbId) * IRO[138].m1))
#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \ #define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
(IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2)) (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \ #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
(IRO[132].base + ((sbId) * IRO[132].m1)) (IRO[136].base + ((sbId) * IRO[136].m1))
#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size) #define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \ #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
(IRO[137].base + ((sbId) * IRO[137].m1)) (IRO[141].base + ((sbId) * IRO[141].m1))
#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size) #define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \ #define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
(IRO[155].base + ((vfId) * IRO[155].m1)) (IRO[159].base + ((vfId) * IRO[159].m1))
#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \ #define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
(IRO[156].base + ((vfId) * IRO[156].m1)) (IRO[160].base + ((vfId) * IRO[160].m1))
#define CSTORM_VF_TO_PF_OFFSET(funcId) \ #define CSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[150].base + ((funcId) * IRO[150].m1)) (IRO[154].base + ((funcId) * IRO[154].m1))
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \ #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
(IRO[203].base + ((pfId) * IRO[203].m1)) (IRO[207].base + ((pfId) * IRO[207].m1))
#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base) #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[101].base + ((assertListEntry) * IRO[101].m1)) (IRO[101].base + ((assertListEntry) * IRO[101].m1))
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
(IRO[201].base + ((pfId) * IRO[201].m1)) (IRO[205].base + ((pfId) * IRO[205].m1))
#define TSTORM_FUNC_EN_OFFSET(funcId) \ #define TSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[103].base + ((funcId) * IRO[103].m1)) (IRO[107].base + ((funcId) * IRO[107].m1))
#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
(IRO[272].base + ((pfId) * IRO[272].m1)) (IRO[278].base + ((pfId) * IRO[278].m1))
#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \ #define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
(IRO[273].base + ((pfId) * IRO[273].m1)) (IRO[279].base + ((pfId) * IRO[279].m1))
#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \ #define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
(IRO[274].base + ((pfId) * IRO[274].m1)) (IRO[280].base + ((pfId) * IRO[280].m1))
#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \ #define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
(IRO[275].base + ((pfId) * IRO[275].m1)) (IRO[281].base + ((pfId) * IRO[281].m1))
#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
(IRO[271].base + ((pfId) * IRO[271].m1)) (IRO[277].base + ((pfId) * IRO[277].m1))
#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
(IRO[270].base + ((pfId) * IRO[270].m1)) (IRO[276].base + ((pfId) * IRO[276].m1))
#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
(IRO[269].base + ((pfId) * IRO[269].m1)) (IRO[275].base + ((pfId) * IRO[275].m1))
#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
(IRO[268].base + ((pfId) * IRO[268].m1)) (IRO[274].base + ((pfId) * IRO[274].m1))
#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
(IRO[278].base + ((pfId) * IRO[278].m1)) (IRO[284].base + ((pfId) * IRO[284].m1))
#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
(IRO[264].base + ((pfId) * IRO[264].m1)) (IRO[270].base + ((pfId) * IRO[270].m1))
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
(IRO[265].base + ((pfId) * IRO[265].m1)) (IRO[271].base + ((pfId) * IRO[271].m1))
#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \ #define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
(IRO[266].base + ((pfId) * IRO[266].m1)) (IRO[272].base + ((pfId) * IRO[272].m1))
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
(IRO[267].base + ((pfId) * IRO[267].m1)) (IRO[273].base + ((pfId) * IRO[273].m1))
#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
(IRO[202].base + ((pfId) * IRO[202].m1)) (IRO[206].base + ((pfId) * IRO[206].m1))
#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ #define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
(IRO[105].base + ((funcId) * IRO[105].m1)) (IRO[109].base + ((funcId) * IRO[109].m1))
#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
(IRO[217].base + ((pfId) * IRO[217].m1)) (IRO[223].base + ((pfId) * IRO[223].m1))
#define TSTORM_VF_TO_PF_OFFSET(funcId) \ #define TSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[104].base + ((funcId) * IRO[104].m1)) (IRO[108].base + ((funcId) * IRO[108].m1))
#define USTORM_AGG_DATA_OFFSET (IRO[206].base) #define USTORM_AGG_DATA_OFFSET (IRO[212].base)
#define USTORM_AGG_DATA_SIZE (IRO[206].size) #define USTORM_AGG_DATA_SIZE (IRO[212].size)
#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base) #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
(IRO[176].base + ((assertListEntry) * IRO[176].m1)) (IRO[180].base + ((assertListEntry) * IRO[180].m1))
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
(IRO[183].base + ((portId) * IRO[183].m1)) (IRO[187].base + ((portId) * IRO[187].m1))
#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
(IRO[319].base + ((pfId) * IRO[319].m1)) (IRO[325].base + ((pfId) * IRO[325].m1))
#define USTORM_FUNC_EN_OFFSET(funcId) \ #define USTORM_FUNC_EN_OFFSET(funcId) \
(IRO[178].base + ((funcId) * IRO[178].m1)) (IRO[182].base + ((funcId) * IRO[182].m1))
#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
(IRO[283].base + ((pfId) * IRO[283].m1)) (IRO[289].base + ((pfId) * IRO[289].m1))
#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
(IRO[284].base + ((pfId) * IRO[284].m1)) (IRO[290].base + ((pfId) * IRO[290].m1))
#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
(IRO[288].base + ((pfId) * IRO[288].m1)) (IRO[294].base + ((pfId) * IRO[294].m1))
#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
(IRO[285].base + ((pfId) * IRO[285].m1)) (IRO[291].base + ((pfId) * IRO[291].m1))
#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
(IRO[281].base + ((pfId) * IRO[281].m1)) (IRO[287].base + ((pfId) * IRO[287].m1))
#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
(IRO[280].base + ((pfId) * IRO[280].m1)) (IRO[286].base + ((pfId) * IRO[286].m1))
#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
(IRO[279].base + ((pfId) * IRO[279].m1)) (IRO[285].base + ((pfId) * IRO[285].m1))
#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
(IRO[282].base + ((pfId) * IRO[282].m1)) (IRO[288].base + ((pfId) * IRO[288].m1))
#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
(IRO[286].base + ((pfId) * IRO[286].m1)) (IRO[292].base + ((pfId) * IRO[292].m1))
#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
(IRO[287].base + ((pfId) * IRO[287].m1)) (IRO[293].base + ((pfId) * IRO[293].m1))
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
(IRO[182].base + ((pfId) * IRO[182].m1)) (IRO[186].base + ((pfId) * IRO[186].m1))
#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
(IRO[180].base + ((funcId) * IRO[180].m1)) (IRO[184].base + ((funcId) * IRO[184].m1))
#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \ #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
(IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \ (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
IRO[209].m2)) IRO[215].m2))
#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \ #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
(IRO[210].base + ((qzoneId) * IRO[210].m1)) (IRO[216].base + ((qzoneId) * IRO[216].m1))
#define USTORM_TPA_BTR_OFFSET (IRO[207].base) #define USTORM_TPA_BTR_OFFSET (IRO[213].base)
#define USTORM_TPA_BTR_SIZE (IRO[207].size) #define USTORM_TPA_BTR_SIZE (IRO[213].size)
#define USTORM_VF_TO_PF_OFFSET(funcId) \ #define USTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[179].base + ((funcId) * IRO[179].m1)) (IRO[183].base + ((funcId) * IRO[183].m1))
#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base) #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base) #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base) #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
...@@ -186,39 +186,39 @@ ...@@ -186,39 +186,39 @@
#define XSTORM_FUNC_EN_OFFSET(funcId) \ #define XSTORM_FUNC_EN_OFFSET(funcId) \
(IRO[47].base + ((funcId) * IRO[47].m1)) (IRO[47].base + ((funcId) * IRO[47].m1))
#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
(IRO[296].base + ((pfId) * IRO[296].m1)) (IRO[302].base + ((pfId) * IRO[302].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
(IRO[299].base + ((pfId) * IRO[299].m1)) (IRO[305].base + ((pfId) * IRO[305].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
(IRO[300].base + ((pfId) * IRO[300].m1)) (IRO[306].base + ((pfId) * IRO[306].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
(IRO[301].base + ((pfId) * IRO[301].m1)) (IRO[307].base + ((pfId) * IRO[307].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
(IRO[302].base + ((pfId) * IRO[302].m1)) (IRO[308].base + ((pfId) * IRO[308].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
(IRO[303].base + ((pfId) * IRO[303].m1)) (IRO[309].base + ((pfId) * IRO[309].m1))
#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
(IRO[304].base + ((pfId) * IRO[304].m1)) (IRO[310].base + ((pfId) * IRO[310].m1))
#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
(IRO[305].base + ((pfId) * IRO[305].m1)) (IRO[311].base + ((pfId) * IRO[311].m1))
#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
(IRO[295].base + ((pfId) * IRO[295].m1)) (IRO[301].base + ((pfId) * IRO[301].m1))
#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
(IRO[294].base + ((pfId) * IRO[294].m1)) (IRO[300].base + ((pfId) * IRO[300].m1))
#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
(IRO[293].base + ((pfId) * IRO[293].m1)) (IRO[299].base + ((pfId) * IRO[299].m1))
#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
(IRO[298].base + ((pfId) * IRO[298].m1)) (IRO[304].base + ((pfId) * IRO[304].m1))
#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
(IRO[297].base + ((pfId) * IRO[297].m1)) (IRO[303].base + ((pfId) * IRO[303].m1))
#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
(IRO[292].base + ((pfId) * IRO[292].m1)) (IRO[298].base + ((pfId) * IRO[298].m1))
#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
(IRO[291].base + ((pfId) * IRO[291].m1)) (IRO[297].base + ((pfId) * IRO[297].m1))
#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
(IRO[290].base + ((pfId) * IRO[290].m1)) (IRO[296].base + ((pfId) * IRO[296].m1))
#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
(IRO[289].base + ((pfId) * IRO[289].m1)) (IRO[295].base + ((pfId) * IRO[295].m1))
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
(IRO[44].base + ((pfId) * IRO[44].m1)) (IRO[44].base + ((pfId) * IRO[44].m1))
#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
...@@ -231,16 +231,19 @@ ...@@ -231,16 +231,19 @@
#define XSTORM_SPQ_PROD_OFFSET(funcId) \ #define XSTORM_SPQ_PROD_OFFSET(funcId) \
(IRO[31].base + ((funcId) * IRO[31].m1)) (IRO[31].base + ((funcId) * IRO[31].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \ #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
(IRO[211].base + ((portId) * IRO[211].m1)) (IRO[217].base + ((portId) * IRO[217].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \ #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
(IRO[212].base + ((portId) * IRO[212].m1)) (IRO[218].base + ((portId) * IRO[218].m1))
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \ #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
(IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \ (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
IRO[214].m2)) IRO[220].m2))
#define XSTORM_VF_TO_PF_OFFSET(funcId) \ #define XSTORM_VF_TO_PF_OFFSET(funcId) \
(IRO[48].base + ((funcId) * IRO[48].m1)) (IRO[48].base + ((funcId) * IRO[48].m1))
#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
/* eth hsi version */
#define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)
/* Ethernet Ring parameters */ /* Ethernet Ring parameters */
#define X_ETH_LOCAL_RING_SIZE 13 #define X_ETH_LOCAL_RING_SIZE 13
#define FIRST_BD_IN_PKT 0 #define FIRST_BD_IN_PKT 0
...@@ -356,6 +359,7 @@ ...@@ -356,6 +359,7 @@
#define XSEMI_CLK1_RESUL_CHIP (1e-3) #define XSEMI_CLK1_RESUL_CHIP (1e-3)
#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6)) #define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
......
drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
View file @ e42780b6
...@@ -2876,8 +2876,8 @@ struct afex_stats { ...@@ -2876,8 +2876,8 @@ struct afex_stats {
}; };
#define BCM_5710_FW_MAJOR_VERSION 7 #define BCM_5710_FW_MAJOR_VERSION 7
#define BCM_5710_FW_MINOR_VERSION 8 #define BCM_5710_FW_MINOR_VERSION 10
#define BCM_5710_FW_REVISION_VERSION 19 #define BCM_5710_FW_REVISION_VERSION 51
#define BCM_5710_FW_ENGINEERING_VERSION 0 #define BCM_5710_FW_ENGINEERING_VERSION 0
#define BCM_5710_FW_COMPILE_FLAGS 1 #define BCM_5710_FW_COMPILE_FLAGS 1
...@@ -3446,6 +3446,7 @@ enum classify_rule { ...@@ -3446,6 +3446,7 @@ enum classify_rule {
CLASSIFY_RULE_OPCODE_MAC, CLASSIFY_RULE_OPCODE_MAC,
CLASSIFY_RULE_OPCODE_VLAN, CLASSIFY_RULE_OPCODE_VLAN,
CLASSIFY_RULE_OPCODE_PAIR, CLASSIFY_RULE_OPCODE_PAIR,
CLASSIFY_RULE_OPCODE_VXLAN,
MAX_CLASSIFY_RULE MAX_CLASSIFY_RULE
}; };
...@@ -3475,7 +3476,8 @@ struct client_init_general_data { ...@@ -3475,7 +3476,8 @@ struct client_init_general_data {
u8 func_id; u8 func_id;
u8 cos; u8 cos;
u8 traffic_type; u8 traffic_type;
u32 reserved0; u8 fp_hsi_ver;
u8 reserved0[3];
}; };
...@@ -3576,7 +3578,7 @@ struct client_init_tx_data { ...@@ -3576,7 +3578,7 @@ struct client_init_tx_data {
u8 tunnel_lso_inc_ip_id; u8 tunnel_lso_inc_ip_id;
u8 refuse_outband_vlan_flg; u8 refuse_outband_vlan_flg;
u8 tunnel_non_lso_pcsum_location; u8 tunnel_non_lso_pcsum_location;
u8 reserved1; u8 tunnel_non_lso_outer_ip_csum_location;
}; };
/* /*
...@@ -3634,6 +3636,11 @@ struct double_regpair { ...@@ -3634,6 +3636,11 @@ struct double_regpair {
u32 regpair1_hi; u32 regpair1_hi;
}; };
/* 2nd parse bd type used in ethernet tx BDs */
enum eth_2nd_parse_bd_type {
ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
MAX_ETH_2ND_PARSE_BD_TYPE
};
/* /*
* Ethernet address typesm used in ethernet tx BDs * Ethernet address typesm used in ethernet tx BDs
...@@ -3718,6 +3725,18 @@ struct eth_classify_vlan_cmd { ...@@ -3718,6 +3725,18 @@ struct eth_classify_vlan_cmd {
__le16 vlan; __le16 vlan;
}; };
/*
* Command for adding/removing a VXLAN classification rule
*/
struct eth_classify_vxlan_cmd {
struct eth_classify_cmd_header header;
__le32 vni;
__le16 inner_mac_lsb;
__le16 inner_mac_mid;
__le16 inner_mac_msb;
__le16 reserved1;
};
/* /*
* union for eth classification rule * union for eth classification rule
*/ */
...@@ -3725,6 +3744,7 @@ union eth_classify_rule_cmd { ...@@ -3725,6 +3744,7 @@ union eth_classify_rule_cmd {
struct eth_classify_mac_cmd mac; struct eth_classify_mac_cmd mac;
struct eth_classify_vlan_cmd vlan; struct eth_classify_vlan_cmd vlan;
struct eth_classify_pair_cmd pair; struct eth_classify_pair_cmd pair;
struct eth_classify_vxlan_cmd vxlan;
}; };
/* /*
...@@ -3902,6 +3922,13 @@ struct eth_filter_rules_ramrod_data { ...@@ -3902,6 +3922,13 @@ struct eth_filter_rules_ramrod_data {
struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
}; };
/* Hsi version */
enum eth_fp_hsi_ver {
ETH_FP_HSI_VER_0,
ETH_FP_HSI_VER_1,
ETH_FP_HSI_VER_2,
MAX_ETH_FP_HSI_VER
};
/* /*
* parameters for eth classification configuration ramrod * parameters for eth classification configuration ramrod
...@@ -3958,20 +3985,28 @@ struct eth_tunnel_data { ...@@ -3958,20 +3985,28 @@ struct eth_tunnel_data {
__le16 dst_mid; __le16 dst_mid;
#endif #endif
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
__le16 reserved0; __le16 fw_ip_hdr_csum;
__le16 dst_hi; __le16 dst_hi;
#elif defined(__LITTLE_ENDIAN) #elif defined(__LITTLE_ENDIAN)
__le16 dst_hi; __le16 dst_hi;
__le16 reserved0; __le16 fw_ip_hdr_csum;
#endif #endif
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
u8 reserved1; u8 flags;
#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0)
#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
u8 ip_hdr_start_inner_w; u8 ip_hdr_start_inner_w;
__le16 pseudo_csum; __le16 pseudo_csum;
#elif defined(__LITTLE_ENDIAN) #elif defined(__LITTLE_ENDIAN)
__le16 pseudo_csum; __le16 pseudo_csum;
u8 ip_hdr_start_inner_w; u8 ip_hdr_start_inner_w;
u8 reserved1; u8 flags;
#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0)
#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
#endif #endif
}; };
...@@ -4059,31 +4094,41 @@ enum eth_rss_mode { ...@@ -4059,31 +4094,41 @@ enum eth_rss_mode {
*/ */
struct eth_rss_update_ramrod_data { struct eth_rss_update_ramrod_data {
u8 rss_engine_id; u8 rss_engine_id;
u8 capabilities; u8 rss_mode;
__le16 capabilities;
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<8)
#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 8
#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY (0x1<<9)
#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY_SHIFT 9
#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY (0x1<<10)
#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY_SHIFT 10
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<11)
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 11
#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0xF<<12)
#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 12
u8 rss_result_mask; u8 rss_result_mask;
u8 rss_mode; u8 reserved3;
__le16 udp_4tuple_dst_port_mask; __le16 reserved4;
__le16 udp_4tuple_dst_port_value;
u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
__le32 rss_key[T_ETH_RSS_KEY]; __le32 rss_key[T_ETH_RSS_KEY];
__le32 echo; __le32 echo;
__le32 reserved3; __le32 reserved5;
}; };
...@@ -4255,10 +4300,10 @@ enum eth_tunnel_lso_inc_ip_id { ...@@ -4255,10 +4300,10 @@ enum eth_tunnel_lso_inc_ip_id {
/* In case tunnel exist and L4 checksum offload, /* In case tunnel exist and L4 checksum offload,
* the pseudo checksum location, on packet or on BD. * the pseudo checksum location, on packet or on BD.
*/ */
enum eth_tunnel_non_lso_pcsum_location { enum eth_tunnel_non_lso_csum_location {
PCSUM_ON_PKT, CSUM_ON_PKT,
PCSUM_ON_BD, CSUM_ON_BD,
MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
}; };
/* /*
...@@ -4305,8 +4350,10 @@ struct eth_tx_start_bd { ...@@ -4305,8 +4350,10 @@ struct eth_tx_start_bd {
__le16 vlan_or_ethertype; __le16 vlan_or_ethertype;
struct eth_tx_bd_flags bd_flags; struct eth_tx_bd_flags bd_flags;
u8 general_data; u8 general_data;
#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) #define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
...@@ -4382,8 +4429,8 @@ struct eth_tx_parse_2nd_bd { ...@@ -4382,8 +4429,8 @@ struct eth_tx_parse_2nd_bd {
__le16 global_data; __le16 global_data;
#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
#define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4) #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
...@@ -4392,9 +4439,14 @@ struct eth_tx_parse_2nd_bd { ...@@ -4392,9 +4439,14 @@ struct eth_tx_parse_2nd_bd {
#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13) #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
__le16 reserved1; u8 bd_type;
#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
u8 reserved3;
u8 tcp_flags; u8 tcp_flags;
#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
...@@ -4412,7 +4464,7 @@ struct eth_tx_parse_2nd_bd { ...@@ -4412,7 +4464,7 @@ struct eth_tx_parse_2nd_bd {
#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
u8 reserved2; u8 reserved4;
u8 tunnel_udp_hdr_start_w; u8 tunnel_udp_hdr_start_w;
u8 fw_ip_hdr_to_payload_w; u8 fw_ip_hdr_to_payload_w;
__le16 fw_ip_csum_wo_len_flags_frag; __le16 fw_ip_csum_wo_len_flags_frag;
...@@ -5200,10 +5252,18 @@ struct function_start_data { ...@@ -5200,10 +5252,18 @@ struct function_start_data {
u8 path_id; u8 path_id;
u8 network_cos_mode; u8 network_cos_mode;
u8 dmae_cmd_id; u8 dmae_cmd_id;
u8 gre_tunnel_mode; u8 tunnel_mode;
u8 gre_tunnel_rss; u8 gre_tunnel_type;
u8 nvgre_clss_en; u8 tunn_clss_en;
__le16 reserved1[2]; u8 inner_gre_rss_en;
u8 sd_accept_mf_clss_fail;
__le16 vxlan_dst_port;
__le16 sd_accept_mf_clss_fail_ethtype;
__le16 sd_vlan_eth_type;
u8 sd_vlan_force_pri_flg;
u8 sd_vlan_force_pri_val;
u8 sd_accept_mf_clss_fail_match_ethtype;
u8 no_added_tags;
}; };
struct function_update_data { struct function_update_data {
...@@ -5220,12 +5280,20 @@ struct function_update_data { ...@@ -5220,12 +5280,20 @@ struct function_update_data {
u8 tx_switch_suspend_change_flg; u8 tx_switch_suspend_change_flg;
u8 tx_switch_suspend; u8 tx_switch_suspend;
u8 echo; u8 echo;
u8 update_tunn_cfg_flg;
u8 tunnel_mode;
u8 gre_tunnel_type;
u8 tunn_clss_en;
u8 inner_gre_rss_en;
__le16 vxlan_dst_port;
u8 sd_vlan_force_pri_change_flg;
u8 sd_vlan_force_pri_flg;
u8 sd_vlan_force_pri_val;
u8 sd_vlan_tag_change_flg;
u8 sd_vlan_eth_type_change_flg;
u8 reserved1; u8 reserved1;
u8 update_gre_cfg_flg; __le16 sd_vlan_tag;
u8 gre_tunnel_mode; __le16 sd_vlan_eth_type;
u8 gre_tunnel_rss;
u8 nvgre_clss_en;
u32 reserved3;
}; };
/* /*
...@@ -5254,17 +5322,9 @@ struct fw_version { ...@@ -5254,17 +5322,9 @@ struct fw_version {
#define __FW_VERSION_RESERVED_SHIFT 4 #define __FW_VERSION_RESERVED_SHIFT 4
}; };
/* GRE RSS Mode */
enum gre_rss_mode {
GRE_OUTER_HEADERS_RSS,
GRE_INNER_HEADERS_RSS,
NVGRE_KEY_ENTROPY_RSS,
MAX_GRE_RSS_MODE
};
/* GRE Tunnel Mode */ /* GRE Tunnel Mode */
enum gre_tunnel_type { enum gre_tunnel_type {
NO_GRE_TUNNEL,
NVGRE_TUNNEL, NVGRE_TUNNEL,
L2GRE_TUNNEL, L2GRE_TUNNEL,
IPGRE_TUNNEL, IPGRE_TUNNEL,
...@@ -5437,6 +5497,7 @@ enum ip_ver { ...@@ -5437,6 +5497,7 @@ enum ip_ver {
* Malicious VF error ID * Malicious VF error ID
*/ */
enum malicious_vf_error_id { enum malicious_vf_error_id {
MALICIOUS_VF_NO_ERROR,
VF_PF_CHANNEL_NOT_READY, VF_PF_CHANNEL_NOT_READY,
ETH_ILLEGAL_BD_LENGTHS, ETH_ILLEGAL_BD_LENGTHS,
ETH_PACKET_TOO_SHORT, ETH_PACKET_TOO_SHORT,
...@@ -5719,10 +5780,15 @@ struct tstorm_vf_zone_data { ...@@ -5719,10 +5780,15 @@ struct tstorm_vf_zone_data {
struct regpair reserved; struct regpair reserved;
}; };
/* Tunnel Mode */
enum tunnel_mode {
TUNN_MODE_NONE,
TUNN_MODE_VXLAN,
TUNN_MODE_GRE,
MAX_TUNNEL_MODE
};
/* /* zone A per-queue data */
* zone A per-queue data
*/
struct ustorm_queue_zone_data { struct ustorm_queue_zone_data {
struct ustorm_eth_rx_producers eth_rx_producers; struct ustorm_eth_rx_producers eth_rx_producers;
struct regpair reserved[3]; struct regpair reserved[3];
......
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
View file @ e42780b6
...@@ -7647,7 +7647,11 @@ static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) ...@@ -7647,7 +7647,11 @@ static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
/* Function parameters */ /* Function parameters */
switch_update_params->suspend = suspend; __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
&switch_update_params->changes);
if (suspend)
__set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
&switch_update_params->changes);
rc = bnx2x_func_state_change(bp, &func_params); rc = bnx2x_func_state_change(bp, &func_params);
......
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
View file @ e42780b6
...@@ -4019,6 +4019,7 @@ static int bnx2x_setup_rss(struct bnx2x *bp, ...@@ -4019,6 +4019,7 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
struct bnx2x_raw_obj *r = &o->raw; struct bnx2x_raw_obj *r = &o->raw;
struct eth_rss_update_ramrod_data *data = struct eth_rss_update_ramrod_data *data =
(struct eth_rss_update_ramrod_data *)(r->rdata); (struct eth_rss_update_ramrod_data *)(r->rdata);
u16 caps = 0;
u8 rss_mode = 0; u8 rss_mode = 0;
int rc; int rc;
...@@ -4042,28 +4043,27 @@ static int bnx2x_setup_rss(struct bnx2x *bp, ...@@ -4042,28 +4043,27 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
/* RSS capabilities */ /* RSS capabilities */
if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags)) if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags))
data->capabilities |= caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags)) if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags))
data->capabilities |= caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags)) if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags))
data->capabilities |= caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags)) if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags))
data->capabilities |= caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags)) if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags))
data->capabilities |= caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags)) if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))
data->capabilities |= caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
if (test_bit(BNX2X_RSS_GRE_INNER_HDRS, &p->rss_flags))
caps |= ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY;
data->capabilities = cpu_to_le16(caps);
/* Hashing mask */ /* Hashing mask */
data->rss_result_mask = p->rss_result_mask; data->rss_result_mask = p->rss_result_mask;
...@@ -4336,6 +4336,8 @@ static void bnx2x_q_fill_init_general_data(struct bnx2x *bp, ...@@ -4336,6 +4336,8 @@ static void bnx2x_q_fill_init_general_data(struct bnx2x *bp,
test_bit(BNX2X_Q_FLG_FCOE, flags) ? test_bit(BNX2X_Q_FLG_FCOE, flags) ?
LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW; LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
gen_data->fp_hsi_ver = ETH_FP_HSI_VERSION;
DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n", DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n",
gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg); gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg);
} }
...@@ -4357,12 +4359,13 @@ static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o, ...@@ -4357,12 +4359,13 @@ static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o,
test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags); test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags);
tx_data->force_default_pri_flg = tx_data->force_default_pri_flg =
test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags); test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags);
tx_data->refuse_outband_vlan_flg =
test_bit(BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, flags);
tx_data->tunnel_lso_inc_ip_id = tx_data->tunnel_lso_inc_ip_id =
test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags); test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags);
tx_data->tunnel_non_lso_pcsum_location = tx_data->tunnel_non_lso_pcsum_location =
test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? PCSUM_ON_PKT : test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT :
PCSUM_ON_BD; CSUM_ON_BD;
tx_data->tx_status_block_id = params->fw_sb_id; tx_data->tx_status_block_id = params->fw_sb_id;
tx_data->tx_sb_index_number = params->sb_cq_index; tx_data->tx_sb_index_number = params->sb_cq_index;
...@@ -5652,8 +5655,11 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp, ...@@ -5652,8 +5655,11 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
rdata->path_id = BP_PATH(bp); rdata->path_id = BP_PATH(bp);
rdata->network_cos_mode = start_params->network_cos_mode; rdata->network_cos_mode = start_params->network_cos_mode;
rdata->gre_tunnel_mode = start_params->gre_tunnel_mode; rdata->tunnel_mode = start_params->tunnel_mode;
rdata->gre_tunnel_rss = start_params->gre_tunnel_rss; rdata->gre_tunnel_type = start_params->gre_tunnel_type;
rdata->inner_gre_rss_en = start_params->inner_gre_rss_en;
rdata->vxlan_dst_port = cpu_to_le16(4789);
rdata->sd_vlan_eth_type = cpu_to_le16(0x8100);
/* No need for an explicit memory barrier here as long we would /* No need for an explicit memory barrier here as long we would
* need to ensure the ordering of writing to the SPQ element * need to ensure the ordering of writing to the SPQ element
...@@ -5680,8 +5686,28 @@ static inline int bnx2x_func_send_switch_update(struct bnx2x *bp, ...@@ -5680,8 +5686,28 @@ static inline int bnx2x_func_send_switch_update(struct bnx2x *bp,
memset(rdata, 0, sizeof(*rdata)); memset(rdata, 0, sizeof(*rdata));
/* Fill the ramrod data with provided parameters */ /* Fill the ramrod data with provided parameters */
rdata->tx_switch_suspend_change_flg = 1; if (test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
rdata->tx_switch_suspend = switch_update_params->suspend; &switch_update_params->changes)) {
rdata->tx_switch_suspend_change_flg = 1;
rdata->tx_switch_suspend =
test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
&switch_update_params->changes);
}
if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
&switch_update_params->changes)) {
rdata->update_tunn_cfg_flg = 1;
if (test_bit(BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
&switch_update_params->changes))
rdata->tunn_clss_en = 1;
if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
&switch_update_params->changes))
rdata->inner_gre_rss_en = 1;
rdata->tunnel_mode = switch_update_params->tunnel_mode;
rdata->gre_tunnel_type = switch_update_params->gre_tunnel_type;
rdata->vxlan_dst_port = cpu_to_le16(4789);
}
rdata->echo = SWITCH_UPDATE; rdata->echo = SWITCH_UPDATE;
/* No need for an explicit memory barrier here as long as we /* No need for an explicit memory barrier here as long as we
......
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
View file @ e42780b6
...@@ -711,6 +711,7 @@ enum { ...@@ -711,6 +711,7 @@ enum {
BNX2X_RSS_IPV6, BNX2X_RSS_IPV6,
BNX2X_RSS_IPV6_TCP, BNX2X_RSS_IPV6_TCP,
BNX2X_RSS_IPV6_UDP, BNX2X_RSS_IPV6_UDP,
BNX2X_RSS_GRE_INNER_HDRS,
}; };
struct bnx2x_config_rss_params { struct bnx2x_config_rss_params {
...@@ -831,6 +832,7 @@ enum { ...@@ -831,6 +832,7 @@ enum {
BNX2X_Q_FLG_ANTI_SPOOF, BNX2X_Q_FLG_ANTI_SPOOF,
BNX2X_Q_FLG_SILENT_VLAN_REM, BNX2X_Q_FLG_SILENT_VLAN_REM,
BNX2X_Q_FLG_FORCE_DEFAULT_PRI, BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN,
BNX2X_Q_FLG_PCSUM_ON_PKT, BNX2X_Q_FLG_PCSUM_ON_PKT,
BNX2X_Q_FLG_TUN_INC_INNER_IP_ID BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
}; };
...@@ -1085,6 +1087,16 @@ struct bnx2x_queue_sp_obj { ...@@ -1085,6 +1087,16 @@ struct bnx2x_queue_sp_obj {
}; };
/********************** Function state update *********************************/ /********************** Function state update *********************************/
/* UPDATE command options */
enum {
BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
};
/* Allowed Function states */ /* Allowed Function states */
enum bnx2x_func_state { enum bnx2x_func_state {
BNX2X_F_STATE_RESET, BNX2X_F_STATE_RESET,
...@@ -1146,18 +1158,25 @@ struct bnx2x_func_start_params { ...@@ -1146,18 +1158,25 @@ struct bnx2x_func_start_params {
/* Function cos mode */ /* Function cos mode */
u8 network_cos_mode; u8 network_cos_mode;
/* NVGRE classification enablement */ /* TUNN_MODE_NONE/TUNN_MODE_VXLAN/TUNN_MODE_GRE */
u8 nvgre_clss_en; u8 tunnel_mode;
/* tunneling classification enablement */
u8 tunn_clss_en;
/* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ /* NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
u8 gre_tunnel_mode; u8 gre_tunnel_type;
/* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ /* Enables Inner GRE RSS on the function, depends on the client RSS
u8 gre_tunnel_rss; * capailities
*/
u8 inner_gre_rss_en;
}; };
struct bnx2x_func_switch_update_params { struct bnx2x_func_switch_update_params {
u8 suspend; unsigned long changes; /* BNX2X_F_UPDATE_XX bits */
u8 tunnel_mode;
u8 gre_tunnel_type;
}; };
struct bnx2x_func_afex_update_params { struct bnx2x_func_afex_update_params {
......
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