Commit e44dde27 authored by Shawn Lin's avatar Shawn Lin Committed by Heiko Stuebner

clk: rockchip: add clock controller for rk1108

Add the clock tree definition and driver for rk1108 SoC.
Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Tested-by: default avatarJacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent aac343eb
...@@ -11,6 +11,7 @@ obj-y += clk-mmc-phase.o ...@@ -11,6 +11,7 @@ obj-y += clk-mmc-phase.o
obj-y += clk-ddr.o obj-y += clk-ddr.o
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-y += clk-rk1108.o
obj-y += clk-rk3036.o obj-y += clk-rk3036.o
obj-y += clk-rk3188.o obj-y += clk-rk3188.o
obj-y += clk-rk3228.o obj-y += clk-rk3228.o
......
This diff is collapsed.
...@@ -34,6 +34,21 @@ struct clk; ...@@ -34,6 +34,21 @@ struct clk;
#define HIWORD_UPDATE(val, mask, shift) \ #define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16)) ((val) << (shift) | (mask) << ((shift) + 16))
/* register positions shared by RK1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
#define RK1108_PLL_CON(x) ((x) * 0x4)
#define RK1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
#define RK1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
#define RK1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
#define RK1108_GLB_SRST_FST 0x1c0
#define RK1108_GLB_SRST_SND 0x1c4
#define RK1108_MISC_CON 0x1cc
#define RK1108_SDMMC_CON0 0x1d8
#define RK1108_SDMMC_CON1 0x1dc
#define RK1108_SDIO_CON0 0x1e0
#define RK1108_SDIO_CON1 0x1e4
#define RK1108_EMMC_CON0 0x1e8
#define RK1108_EMMC_CON1 0x1ec
#define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40 #define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
......
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