Commit e483fe34 authored by Sheetal's avatar Sheetal Committed by Thierry Reding

arm64: tegra: Update AHUB clock parent and rate on Tegra234

I2S data sanity tests fail beyond a bit clock frequency of 6.144MHz.
This happens because the AHUB clock rate is too low and it shows
9.83MHz on boot.

The maximum rate of PLLA_OUT0 is 49.152MHz and is used to serve I/O
clocks. It is recommended that AHUB clock operates higher than this.
Thus fix this by using PLLP_OUT0 as parent clock for AHUB instead of
PLLA_OUT0 and fix the rate to 81.6MHz.

Fixes: dc94a94d ("arm64: tegra: Add audio devices on Tegra234")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSheetal <sheetal@nvidia.com>
Signed-off-by: default avatarSameer Pujar <spujar@nvidia.com>
Reviewed-by: default avatarMohan Kumar D <mkumard@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 06c2afb8
...@@ -180,7 +180,8 @@ tegra_ahub: ahub@2900800 { ...@@ -180,7 +180,8 @@ tegra_ahub: ahub@2900800 {
clocks = <&bpmp TEGRA234_CLK_AHUB>; clocks = <&bpmp TEGRA234_CLK_AHUB>;
clock-names = "ahub"; clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clock-rates = <81600000>;
status = "disabled"; status = "disabled";
#address-cells = <2>; #address-cells = <2>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment