Commit e4e06a50 authored by Lars Povlsen's avatar Lars Povlsen Committed by Arnd Bergmann

arm64: dts: sparx5: Add Sparx5 SoC DPLL clock

This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.

Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.comSigned-off-by: default avatarLars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 39c8378a
...@@ -72,21 +72,30 @@ timer { ...@@ -72,21 +72,30 @@ timer {
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
}; };
clocks: clocks { lcpll_clk: lcpll-clk {
#address-cells = <2>; compatible = "fixed-clock";
#size-cells = <1>; #clock-cells = <0>;
ranges; clock-frequency = <2500000000>;
};
clks: clock-controller@61110000c {
compatible = "microchip,sparx5-dpll";
#clock-cells = <1>;
clocks = <&lcpll_clk>;
reg = <0x6 0x1110000c 0x24>;
};
ahb_clk: ahb-clk { ahb_clk: ahb-clk {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <250000000>; clock-frequency = <250000000>;
}; };
sys_clk: sys-clk { sys_clk: sys-clk {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <625000000>; clock-frequency = <625000000>;
}; };
};
axi: axi@600000000 { axi: axi@600000000 {
compatible = "simple-bus"; compatible = "simple-bus";
...@@ -161,8 +170,6 @@ uart2_pins: uart2-pins { ...@@ -161,8 +170,6 @@ uart2_pins: uart2-pins {
pins = "GPIO_26", "GPIO_27"; pins = "GPIO_26", "GPIO_27";
function = "uart2"; function = "uart2";
}; };
}; };
}; };
}; };
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