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Commit e503606c authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (40 commits)
  [MIPS] Yosemite: Fix missing parens in SERIAL_READ_1 macro
  [MIPS] Fix warnings in run_uncached on 32bit kernel
  [MIPS] Comment fix
  [MIPS] MT: Nuke duplicate mips_mt_regdump() prototype.
  [MIPS] Alchemy:  Fix PCI-memory access
  [MIPS] Move .set reorder out of conditional code
  [MIPS] Check FCSR for pending interrupts before restoring from a context.
  [MIPS] Jaguar ATX: Fix large number of warnings.
  [MIPS] Jaguar: Fix MAC address detection after platform_device conversion.
  [MIPS] SMTC: Make a bunch of functions and variables static.
  [MIPS] Use compat_sys_pselect6
  [MIPS] SMTC: Cleanup idle hook invocation.
  [MIPS] SELinux: Add security hooks to mips-mt {get,set}affinity
  [MIPS] IRIX: Linux coding style cleanups.
  [MIPS] PB1100: Fix pile of warnings
  [MIPS] Alchemy: Fix bunch of warnings
  [MIPS] Whitespace cleanups.
  [MIPS] Alchemy: Fix bunch more warnings.
  [MIPS] Use ARRAY_SIZE macro when appropriate
  [MIPS] Fix some whitespace damage
  ...
parents 76c32956 d390008e
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Showing with 1111 additions and 1052 deletions
arch/mips/Kconfig
View file @ e503606c
......@@ -575,6 +575,7 @@ config SGI_IP27
select DMA_IP27
select EARLY_PRINTK
select HW_HAS_PCI
select NR_CPUS_DEFAULT_64
select PCI_DOMAINS
select SYS_HAS_CPU_R10000
select SYS_SUPPORTS_64BIT_KERNEL
......@@ -612,6 +613,7 @@ config SIBYTE_BIGSUR
bool "Sibyte BCM91480B-BigSur"
select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_4
select PCI_DOMAINS
select SIBYTE_BCM1x80
select SWAP_IO_SPACE
......@@ -623,6 +625,7 @@ config SIBYTE_SWARM
bool "Sibyte BCM91250A-SWARM"
select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
......@@ -635,6 +638,7 @@ config SIBYTE_SENTOSA
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
......@@ -668,6 +672,7 @@ config SIBYTE_PTSWARM
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
......@@ -680,6 +685,7 @@ config SIBYTE_LITTLESUR
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
......@@ -790,23 +796,6 @@ config TOSHIBA_RBTX4938
endchoice
config KEXEC
bool "Kexec system call (EXPERIMENTAL)"
depends on EXPERIMENTAL
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
but it is indepedent of the system firmware. And like a reboot
you can start any kernel with it, not just Linux.
The name comes from the similiarity to the exec system call.
It is an ongoing process to be certain the hardware in a machine
is properly shutdown, so do not be surprised if this code does not
initially work for you. It may help to enable device hotplugging
support. As of this writing the exact hardware interface is
strongly in flux, so no good recommendation can be made.
source "arch/mips/ddb5xxx/Kconfig"
source "arch/mips/gt64120/ev64120/Kconfig"
source "arch/mips/jazz/Kconfig"
......@@ -1541,6 +1530,8 @@ config MIPS_MT_SMTC
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_SRS
select MIPS_MT
select NR_CPUS_DEFAULT_2
select NR_CPUS_DEFAULT_8
select SMP
select SYS_SUPPORTS_SMP
help
......@@ -1756,13 +1747,34 @@ config SMP
config SYS_SUPPORTS_SMP
bool
config NR_CPUS_DEFAULT_2
bool
config NR_CPUS_DEFAULT_4
bool
config NR_CPUS_DEFAULT_8
bool
config NR_CPUS_DEFAULT_16
bool
config NR_CPUS_DEFAULT_32
bool
config NR_CPUS_DEFAULT_64
bool
config NR_CPUS
int "Maximum number of CPUs (2-64)"
range 2 64
depends on SMP
default "64" if SGI_IP27
default "2"
default "8" if MIPS_MT_SMTC
default "2" if NR_CPUS_DEFAULT_2
default "4" if NR_CPUS_DEFAULT_4
default "8" if NR_CPUS_DEFAULT_8
default "16" if NR_CPUS_DEFAULT_16
default "32" if NR_CPUS_DEFAULT_32
default "64" if NR_CPUS_DEFAULT_64
help
This allows you to specify the maximum number of CPUs which this
kernel will support. The maximum supported value is 32 for 32-bit
......@@ -1859,6 +1871,40 @@ config MIPS_INSANE_LARGE
This will result in additional memory usage, so it is not
recommended for normal users.
config KEXEC
bool "Kexec system call (EXPERIMENTAL)"
depends on EXPERIMENTAL
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
but it is indepedent of the system firmware. And like a reboot
you can start any kernel with it, not just Linux.
The name comes from the similiarity to the exec system call.
It is an ongoing process to be certain the hardware in a machine
is properly shutdown, so do not be surprised if this code does not
initially work for you. It may help to enable device hotplugging
support. As of this writing the exact hardware interface is
strongly in flux, so no good recommendation can be made.
config SECCOMP
bool "Enable seccomp to safely compute untrusted bytecode"
depends on PROC_FS && BROKEN
default y
help
This kernel feature is useful for number crunching applications
that may need to compute untrusted bytecode during their
execution. By using pipes or other transports made available to
the process as file descriptors supporting the read/write
syscalls, it's possible to isolate those applications in
their own address space using seccomp. Once seccomp is
enabled via /proc/<pid>/seccomp, it cannot be disabled
and the task is only allowed to execute a few safe syscalls
defined by each seccomp mode.
If unsure, say Y. Only embedded should say N here.
endmenu
config RWSEM_GENERIC_SPINLOCK
......@@ -2025,23 +2071,6 @@ config BINFMT_ELF32
bool
default y if MIPS32_O32 || MIPS32_N32
config SECCOMP
bool "Enable seccomp to safely compute untrusted bytecode"
depends on PROC_FS && BROKEN
default y
help
This kernel feature is useful for number crunching applications
that may need to compute untrusted bytecode during their
execution. By using pipes or other transports made available to
the process as file descriptors supporting the read/write
syscalls, it's possible to isolate those applications in
their own address space using seccomp. Once seccomp is
enabled via /proc/<pid>/seccomp, it cannot be disabled
and the task is only allowed to execute a few safe syscalls
defined by each seccomp mode.
If unsure, say Y. Only embedded should say N here.
config PM
bool "Power Management support (EXPERIMENTAL)"
depends on EXPERIMENTAL && SOC_AU1X00
......
arch/mips/arc/identify.c
View file @ e503606c
......@@ -77,7 +77,7 @@ static struct smatch * __init string_to_mach(const char *s)
{
int i;
for (i = 0; i < (sizeof(mach_table) / sizeof (mach_table[0])); i++) {
for (i = 0; i < ARRAY_SIZE(mach_table); i++) {
if (!strcmp(s, mach_table[i].arcname))
return &mach_table[i];
}
......
arch/mips/arc/memory.c
View file @ e503606c
......@@ -141,30 +141,20 @@ void __init prom_meminit(void)
}
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
unsigned long freed = 0;
unsigned long addr;
int i;
if (prom_flags & PROM_FLAG_DONT_FREE_TEMP)
return 0;
return;
for (i = 0; i < boot_mem_map.nr_map; i++) {
if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
continue;
addr = boot_mem_map.map[i].addr;
while (addr < boot_mem_map.map[i].addr
+ boot_mem_map.map[i].size) {
ClearPageReserved(virt_to_page(__va(addr)));
init_page_count(virt_to_page(__va(addr)));
free_page((unsigned long)__va(addr));
addr += PAGE_SIZE;
freed += PAGE_SIZE;
free_init_pages("prom memory",
addr, addr + boot_mem_map.map[i].size);
}
}
printk(KERN_INFO "Freeing prom memory: %ldkb freed\n", freed >> 10);
return freed;
}
arch/mips/au1000/common/irq.c
View file @ e503606c
......@@ -233,7 +233,7 @@ void restore_local_and_enable(int controller, unsigned long mask)
static struct irq_chip rise_edge_irq_type = {
.typename = "Au1000 Rise Edge",
.name = "Au1000 Rise Edge",
.ack = mask_and_ack_rise_edge_irq,
.mask = local_disable_irq,
.mask_ack = mask_and_ack_rise_edge_irq,
......@@ -242,7 +242,7 @@ static struct irq_chip rise_edge_irq_type = {
};
static struct irq_chip fall_edge_irq_type = {
.typename = "Au1000 Fall Edge",
.name = "Au1000 Fall Edge",
.ack = mask_and_ack_fall_edge_irq,
.mask = local_disable_irq,
.mask_ack = mask_and_ack_fall_edge_irq,
......@@ -251,7 +251,7 @@ static struct irq_chip fall_edge_irq_type = {
};
static struct irq_chip either_edge_irq_type = {
.typename = "Au1000 Rise or Fall Edge",
.name = "Au1000 Rise or Fall Edge",
.ack = mask_and_ack_either_edge_irq,
.mask = local_disable_irq,
.mask_ack = mask_and_ack_either_edge_irq,
......@@ -260,7 +260,7 @@ static struct irq_chip either_edge_irq_type = {
};
static struct irq_chip level_irq_type = {
.typename = "Au1000 Level",
.name = "Au1000 Level",
.ack = mask_and_ack_level_irq,
.mask = local_disable_irq,
.mask_ack = mask_and_ack_level_irq,
......
arch/mips/au1000/common/pci.c
View file @ e503606c
......@@ -76,14 +76,18 @@ static int __init au1x_pci_setup(void)
}
#ifdef CONFIG_DMA_NONCOHERENT
{
/*
* Set the NC bit in controller for Au1500 pre-AC silicon
*/
u32 prid = read_c0_prid();
if ( (prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
au_writel( 1<<16 | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG);
if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
Au1500_PCI_CFG);
printk("Non-coherent PCI accesses enabled\n");
}
}
#endif
set_io_port_base(virt_io_addr);
......
arch/mips/au1000/common/prom.c
View file @ e503606c
......@@ -149,9 +149,8 @@ int get_ethernet_addr(char *ethernet_addr)
return 0;
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
EXPORT_SYMBOL(prom_getcmdline);
......
arch/mips/au1000/common/setup.c
View file @ e503606c
......@@ -141,17 +141,20 @@ void __init plat_mem_setup(void)
/* This routine should be valid for all Au1x based boards */
phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
u32 start, end;
/* Don't fixup 36 bit addresses */
if ((phys_addr >> 32) != 0) return phys_addr;
if ((phys_addr >> 32) != 0)
return phys_addr;
#ifdef CONFIG_PCI
{
u32 start, end;
start = (u32)Au1500_PCI_MEM_START;
end = (u32)Au1500_PCI_MEM_END;
/* check for pci memory window */
if ((phys_addr >= start) && ((phys_addr + size) < end)) {
return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
if ((phys_addr >= start) && ((phys_addr + size) < end))
return (phys_t)
((phys_addr - start) + Au1500_PCI_MEM_START);
}
#endif
......
arch/mips/au1000/pb1100/board_setup.c
View file @ e503606c
......@@ -47,8 +47,7 @@ void board_reset (void)
void __init board_setup(void)
{
u32 pin_func;
u32 sys_freqctrl, sys_clksrc;
volatile void __iomem * base = (volatile void __iomem *) 0xac000000UL;
// set AUX clock to 12MHz * 8 = 96 MHz
au_writel(8, SYS_AUXPLL);
......@@ -56,6 +55,9 @@ void __init board_setup(void)
udelay(100);
#ifdef CONFIG_USB_OHCI
{
u32 pin_func, sys_freqctrl, sys_clksrc;
// configure pins GPIO[14:9] as GPIO
pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x80);
......@@ -95,19 +97,20 @@ void __init board_setup(void)
// 2nd USB port is USB host
pin_func |= 0x8000;
au_writel(pin_func, SYS_PINFUNC);
}
#endif // defined (CONFIG_USB_OHCI)
/* Enable sys bus clock divider when IDLE state or no bus activity. */
au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
// Enable the RTC if not already enabled
if (!(readb(0xac000028) & 0x20)) {
writeb(readb(0xac000028) | 0x20, 0xac000028);
if (!(readb(base + 0x28) & 0x20)) {
writeb(readb(base + 0x28) | 0x20, base + 0x28);
au_sync();
}
// Put the clock in BCD mode
if (readb(0xac00002C) & 0x4) { /* reg B */
writeb(readb(0xac00002c) & ~0x4, 0xac00002c);
if (readb(base + 0x2C) & 0x4) { /* reg B */
writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
au_sync();
}
}
arch/mips/au1000/pb1200/irqmap.c
View file @ e503606c
......@@ -137,33 +137,20 @@ static void pb1200_shutdown_irq( unsigned int irq_nr )
return;
}
static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
{
pb1200_disable_irq( irq_nr );
}
static void pb1200_end_irq(unsigned int irq_nr)
{
if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
pb1200_enable_irq(irq_nr);
}
}
static struct irq_chip external_irq_type =
{
#ifdef CONFIG_MIPS_PB1200
"Pb1200 Ext",
.name = "Pb1200 Ext",
#endif
#ifdef CONFIG_MIPS_DB1200
"Db1200 Ext",
.name = "Db1200 Ext",
#endif
pb1200_startup_irq,
pb1200_shutdown_irq,
pb1200_enable_irq,
pb1200_disable_irq,
pb1200_mask_and_ack_irq,
pb1200_end_irq,
NULL
.startup = pb1200_startup_irq,
.shutdown = pb1200_shutdown_irq,
.ack = pb1200_disable_irq,
.mask = pb1200_disable_irq,
.mask_ack = pb1200_disable_irq,
.unmask = pb1200_enable_irq,
};
void _board_init_irq(void)
......@@ -172,7 +159,8 @@ void _board_init_irq(void)
for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
{
irq_desc[irq_nr].chip = &external_irq_type;
set_irq_chip_and_handler(irq_nr, &external_irq_type,
handle_level_irq);
pb1200_disable_irq(irq_nr);
}
......
arch/mips/basler/excite/excite_irq.c
View file @ e503606c
......@@ -47,9 +47,9 @@ extern asmlinkage void excite_handle_int(void);
*/
void __init arch_init_irq(void)
{
mips_cpu_irq_init(0);
rm7k_cpu_irq_init(8);
rm9k_cpu_irq_init(12);
mips_cpu_irq_init();
rm7k_cpu_irq_init();
rm9k_cpu_irq_init();
#ifdef CONFIG_KGDB
excite_kgdb_init();
......
arch/mips/cobalt/irq.c
View file @ e503606c
......@@ -104,7 +104,7 @@ void __init arch_init_irq(void)
GT_WRITE(GT_INTRMASK_OFS, 0);
init_i8259_irqs(); /* 0 ... 15 */
mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
mips_cpu_irq_init(); /* 16 ... 23 */
/*
* Mask all cpu interrupts
......
arch/mips/cobalt/setup.c
View file @ e503606c
......@@ -204,8 +204,7 @@ void __init prom_init(void)
add_memory_region(0x0, memsz, BOOT_MEM_RAM);
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
/* Nothing to do! */
return 0;
}
arch/mips/ddb5xxx/common/prom.c
View file @ e503606c
......@@ -59,9 +59,8 @@ void __init prom_init(void)
#endif
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
#if defined(CONFIG_DDB5477)
......
arch/mips/ddb5xxx/ddb5477/irq.c
View file @ e503606c
......@@ -17,6 +17,7 @@
#include <linux/ptrace.h>
#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
#include <asm/debug.h>
......@@ -73,7 +74,6 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
}
extern void vrc5477_irq_init(u32 base);
extern void mips_cpu_irq_init(u32 base);
static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
void __init arch_init_irq(void)
......@@ -125,7 +125,7 @@ void __init arch_init_irq(void)
/* init all controllers */
init_i8259_irqs();
mips_cpu_irq_init(CPU_IRQ_BASE);
mips_cpu_irq_init();
vrc5477_irq_init(VRC5477_IRQ_BASE);
......@@ -146,8 +146,7 @@ u8 i8259_interrupt_ack(void)
irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
ddb_out32(DDB_PCIINIT10, reg);
/* i8259.c set the base vector to be 0x0 */
return irq + I8259_IRQ_BASE;
return irq;
}
/*
* the first level int-handler will jump here if it is a vrc5477 irq
......@@ -177,7 +176,7 @@ static void vrc5477_irq_dispatch(void)
/* check for i8259 interrupts */
if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
int i8259_irq = i8259_interrupt_ack();
do_IRQ(I8259_IRQ_BASE + i8259_irq);
do_IRQ(i8259_irq);
return;
}
}
......
arch/mips/ddb5xxx/ddb5477/irq_5477.c
View file @ e503606c
......@@ -82,7 +82,7 @@ vrc5477_irq_end(unsigned int irq)
}
struct irq_chip vrc5477_irq_controller = {
.typename = "vrc5477_irq",
.name = "vrc5477_irq",
.ack = vrc5477_irq_ack,
.mask = vrc5477_irq_disable,
.mask_ack = vrc5477_irq_ack,
......
arch/mips/dec/ioasic-irq.c
View file @ e503606c
......@@ -62,7 +62,7 @@ static inline void end_ioasic_irq(unsigned int irq)
}
static struct irq_chip ioasic_irq_type = {
.typename = "IO-ASIC",
.name = "IO-ASIC",
.ack = ack_ioasic_irq,
.mask = mask_ioasic_irq,
.mask_ack = ack_ioasic_irq,
......@@ -84,7 +84,7 @@ static inline void end_ioasic_dma_irq(unsigned int irq)
}
static struct irq_chip ioasic_dma_irq_type = {
.typename = "IO-ASIC-DMA",
.name = "IO-ASIC-DMA",
.ack = ack_ioasic_dma_irq,
.mask = mask_ioasic_dma_irq,
.mask_ack = ack_ioasic_dma_irq,
......
arch/mips/dec/kn02-irq.c
View file @ e503606c
......@@ -58,7 +58,7 @@ static void ack_kn02_irq(unsigned int irq)
}
static struct irq_chip kn02_irq_type = {
.typename = "KN02-CSR",
.name = "KN02-CSR",
.ack = ack_kn02_irq,
.mask = mask_kn02_irq,
.mask_ack = ack_kn02_irq,
......
arch/mips/dec/prom/memory.c
View file @ e503606c
......@@ -92,9 +92,9 @@ void __init prom_meminit(u32 magic)
rex_setup_memory_region();
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
unsigned long addr, end;
unsigned long end;
/*
* Free everything below the kernel itself but leave
......@@ -114,16 +114,5 @@ unsigned long __init prom_free_prom_memory(void)
#endif
end = __pa(&_text);
addr = PAGE_SIZE;
while (addr < end) {
ClearPageReserved(virt_to_page(__va(addr)));
init_page_count(virt_to_page(__va(addr)));
free_page((unsigned long)__va(addr));
addr += PAGE_SIZE;
}
printk("Freeing unused PROM memory: %ldkb freed\n",
(end - PAGE_SIZE) >> 10);
return end - PAGE_SIZE;
free_init_pages("unused PROM memory", PAGE_SIZE, end);
}
arch/mips/dec/setup.c
View file @ e503606c
......@@ -234,7 +234,7 @@ static void __init dec_init_kn01(void)
memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
sizeof(kn01_cpu_mask_nr_tbl));
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
mips_cpu_irq_init();
} /* dec_init_kn01 */
......@@ -309,7 +309,7 @@ static void __init dec_init_kn230(void)
memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
sizeof(kn230_cpu_mask_nr_tbl));
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
mips_cpu_irq_init();
} /* dec_init_kn230 */
......@@ -403,7 +403,7 @@ static void __init dec_init_kn02(void)
memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
sizeof(kn02_asic_mask_nr_tbl));
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
mips_cpu_irq_init();
init_kn02_irqs(KN02_IRQ_BASE);
} /* dec_init_kn02 */
......@@ -504,7 +504,7 @@ static void __init dec_init_kn02ba(void)
memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
sizeof(kn02ba_asic_mask_nr_tbl));
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
mips_cpu_irq_init();
init_ioasic_irqs(IO_IRQ_BASE);
} /* dec_init_kn02ba */
......@@ -601,7 +601,7 @@ static void __init dec_init_kn02ca(void)
memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
sizeof(kn02ca_asic_mask_nr_tbl));
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
mips_cpu_irq_init();
init_ioasic_irqs(IO_IRQ_BASE);
} /* dec_init_kn02ca */
......@@ -702,7 +702,7 @@ static void __init dec_init_kn03(void)
memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
sizeof(kn03_asic_mask_nr_tbl));
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
mips_cpu_irq_init();
init_ioasic_irqs(IO_IRQ_BASE);
} /* dec_init_kn03 */
......
arch/mips/emma2rh/common/irq_emma2rh.c
View file @ e503606c
......@@ -57,7 +57,7 @@ static void emma2rh_irq_disable(unsigned int irq)
}
struct irq_chip emma2rh_irq_controller = {
.typename = "emma2rh_irq",
.name = "emma2rh_irq",
.ack = emma2rh_irq_disable,
.mask = emma2rh_irq_disable,
.mask_ack = emma2rh_irq_disable,
......
arch/mips/emma2rh/markeins/irq.c
View file @ e503606c
......@@ -106,7 +106,7 @@ void __init arch_init_irq(void)
emma2rh_irq_init(EMMA2RH_IRQ_BASE);
emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
mips_cpu_irq_init(CPU_IRQ_BASE);
mips_cpu_irq_init();
/* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
......
arch/mips/emma2rh/markeins/irq_markeins.c
View file @ e503606c
......@@ -49,7 +49,7 @@ static void emma2rh_sw_irq_disable(unsigned int irq)
}
struct irq_chip emma2rh_sw_irq_controller = {
.typename = "emma2rh_sw_irq",
.name = "emma2rh_sw_irq",
.ack = emma2rh_sw_irq_disable,
.mask = emma2rh_sw_irq_disable,
.mask_ack = emma2rh_sw_irq_disable,
......@@ -115,7 +115,7 @@ static void emma2rh_gpio_irq_end(unsigned int irq)
}
struct irq_chip emma2rh_gpio_irq_controller = {
.typename = "emma2rh_gpio_irq",
.name = "emma2rh_gpio_irq",
.ack = emma2rh_gpio_irq_ack,
.mask = emma2rh_gpio_irq_disable,
.mask_ack = emma2rh_gpio_irq_ack,
......
arch/mips/gt64120/ev64120/irq.c
View file @ e503606c
......@@ -88,7 +88,7 @@ static void end_ev64120_irq(unsigned int irq)
}
static struct irq_chip ev64120_irq_type = {
.typename = "EV64120",
.name = "EV64120",
.ack = disable_ev64120_irq,
.mask = disable_ev64120_irq,
.mask_ack = disable_ev64120_irq,
......
arch/mips/gt64120/ev64120/setup.c
View file @ e503606c
......@@ -59,9 +59,8 @@ extern void galileo_machine_power_off(void);
*/
extern struct pci_ops galileo_pci_ops;
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
/*
......
arch/mips/gt64120/momenco_ocelot/dbg_io.c
View file @ e503606c
#ifdef CONFIG_KGDB
#include <asm/serial.h> /* For the serial port location and base baud */
/* --- CONFIG --- */
......@@ -121,5 +119,3 @@ int putDebugChar(uint8 byte)
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
arch/mips/gt64120/momenco_ocelot/irq.c
View file @ e503606c
......@@ -90,6 +90,6 @@ void __init arch_init_irq(void)
clear_c0_status(ST0_IM);
local_irq_disable();
mips_cpu_irq_init(0);
rm7k_cpu_irq_init(8);
mips_cpu_irq_init();
rm7k_cpu_irq_init();
}
arch/mips/gt64120/momenco_ocelot/prom.c
View file @ e503606c
......@@ -67,7 +67,6 @@ void __init prom_init(void)
add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
arch/mips/gt64120/wrppmc/irq.c
View file @ e503606c
......@@ -63,7 +63,7 @@ void gt64120_init_pic(void)
void __init arch_init_irq(void)
{
/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
mips_cpu_irq_init(0);
mips_cpu_irq_init();
gt64120_init_pic();
}
arch/mips/gt64120/wrppmc/setup.c
View file @ e503606c
......@@ -93,9 +93,8 @@ void __init wrppmc_early_printk(const char *fmt, ...)
}
#endif /* WRPPMC_EARLY_DEBUG */
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
#ifdef CONFIG_SERIAL_8250
......
arch/mips/jazz/irq.c
View file @ e503606c
......@@ -40,7 +40,7 @@ void disable_r4030_irq(unsigned int irq)
}
static struct irq_chip r4030_irq_type = {
.typename = "R4030",
.name = "R4030",
.ack = disable_r4030_irq,
.mask = disable_r4030_irq,
.mask_ack = disable_r4030_irq,
......
arch/mips/jmr3927/common/prom.c
View file @ e503606c
......@@ -75,7 +75,6 @@ void __init prom_init_cmdline(void)
*cp = '\0';
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
arch/mips/jmr3927/rbhma3100/irq.c
View file @ e503606c
......@@ -439,7 +439,7 @@ void __init arch_init_irq(void)
}
static struct irq_chip jmr3927_irq_controller = {
.typename = "jmr3927_irq",
.name = "jmr3927_irq",
.ack = jmr3927_irq_ack,
.mask = jmr3927_irq_disable,
.mask_ack = jmr3927_irq_ack,
......
arch/mips/jmr3927/rbhma3100/setup.c
View file @ e503606c
......@@ -434,7 +434,7 @@ void __init tx3927_setup(void)
/* DMA */
tx3927_dmaptr->mcr = 0;
for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
/* reset channel */
tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
tx3927_dmaptr->ch[i].ccr = 0;
......
arch/mips/kernel/asm-offsets.c
View file @ e503606c
......@@ -234,10 +234,6 @@ void output_mm_defines(void)
constant("#define _PMD_SHIFT ", PMD_SHIFT);
constant("#define _PGDIR_SHIFT ", PGDIR_SHIFT);
linefeed;
constant("#define _PGD_ORDER ", PGD_ORDER);
constant("#define _PMD_ORDER ", PMD_ORDER);
constant("#define _PTE_ORDER ", PTE_ORDER);
linefeed;
constant("#define _PTRS_PER_PGD ", PTRS_PER_PGD);
constant("#define _PTRS_PER_PMD ", PTRS_PER_PMD);
constant("#define _PTRS_PER_PTE ", PTRS_PER_PTE);
......
arch/mips/kernel/head.S
View file @ e503606c
......@@ -231,28 +231,3 @@ NESTED(smp_bootstrap, 16, sp)
#endif /* CONFIG_SMP */
__FINIT
.comm kernelsp, NR_CPUS * 8, 8
.comm pgd_current, NR_CPUS * 8, 8
.comm fw_arg0, SZREG, SZREG # firmware arguments
.comm fw_arg1, SZREG, SZREG
.comm fw_arg2, SZREG, SZREG
.comm fw_arg3, SZREG, SZREG
.macro page name, order
.comm \name, (_PAGE_SIZE << \order), (_PAGE_SIZE << \order)
.endm
/*
* On 64-bit we've got three-level pagetables with a slightly
* different layout ...
*/
page swapper_pg_dir, _PGD_ORDER
#ifdef CONFIG_64BIT
#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64)
page module_pg_dir, _PGD_ORDER
#endif
page invalid_pmd_table, _PMD_ORDER
#endif
page invalid_pte_table, _PTE_ORDER
arch/mips/kernel/i8259.c
View file @ e503606c
......@@ -54,9 +54,11 @@ static unsigned int cached_irq_mask = 0xffff;
void disable_8259A_irq(unsigned int irq)
{
unsigned int mask = 1 << irq;
unsigned int mask;
unsigned long flags;
irq -= I8259A_IRQ_BASE;
mask = 1 << irq;
spin_lock_irqsave(&i8259A_lock, flags);
cached_irq_mask |= mask;
if (irq & 8)
......@@ -68,9 +70,11 @@ void disable_8259A_irq(unsigned int irq)
void enable_8259A_irq(unsigned int irq)
{
unsigned int mask = ~(1 << irq);
unsigned int mask;
unsigned long flags;
irq -= I8259A_IRQ_BASE;
mask = ~(1 << irq);
spin_lock_irqsave(&i8259A_lock, flags);
cached_irq_mask &= mask;
if (irq & 8)
......@@ -82,10 +86,12 @@ void enable_8259A_irq(unsigned int irq)
int i8259A_irq_pending(unsigned int irq)
{
unsigned int mask = 1 << irq;
unsigned int mask;
unsigned long flags;
int ret;
irq -= I8259A_IRQ_BASE;
mask = 1 << irq;
spin_lock_irqsave(&i8259A_lock, flags);
if (irq < 8)
ret = inb(PIC_MASTER_CMD) & mask;
......@@ -134,9 +140,11 @@ static inline int i8259A_irq_real(unsigned int irq)
*/
void mask_and_ack_8259A(unsigned int irq)
{
unsigned int irqmask = 1 << irq;
unsigned int irqmask;
unsigned long flags;
irq -= I8259A_IRQ_BASE;
irqmask = 1 << irq;
spin_lock_irqsave(&i8259A_lock, flags);
/*
* Lightweight spurious IRQ detection. We do not want
......@@ -322,8 +330,8 @@ void __init init_i8259_irqs (void)
init_8259A(0);
for (i = 0; i < 16; i++)
for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++)
set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
setup_irq(PIC_CASCADE_IR, &irq2);
setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
}
arch/mips/kernel/irixelf.c
View file @ e503606c
......@@ -10,6 +10,8 @@
* Copyright (C) 1996 - 2004 David S. Miller <dm@engr.sgi.com>
* Copyright (C) 2004 - 2005 Steven J. Hill <sjhill@realitydiluted.com>
*/
#undef DEBUG
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/stat.h>
......@@ -40,8 +42,6 @@
#include <linux/elf.h>
#undef DEBUG
static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs);
static int load_irix_library(struct file *);
static int irix_core_dump(long signr, struct pt_regs * regs,
......@@ -52,55 +52,86 @@ static struct linux_binfmt irix_format = {
irix_core_dump, PAGE_SIZE
};
#ifdef DEBUG
/* Debugging routines. */
static char *get_elf_p_type(Elf32_Word p_type)
{
int i = (int) p_type;
switch(i) {
case PT_NULL: return("PT_NULL"); break;
case PT_LOAD: return("PT_LOAD"); break;
case PT_DYNAMIC: return("PT_DYNAMIC"); break;
case PT_INTERP: return("PT_INTERP"); break;
case PT_NOTE: return("PT_NOTE"); break;
case PT_SHLIB: return("PT_SHLIB"); break;
case PT_PHDR: return("PT_PHDR"); break;
case PT_LOPROC: return("PT_LOPROC/REGINFO"); break;
case PT_HIPROC: return("PT_HIPROC"); break;
default: return("PT_BOGUS"); break;
#ifdef DEBUG
switch (p_type) {
case PT_NULL:
return "PT_NULL";
break;
case PT_LOAD:
return "PT_LOAD";
break;
case PT_DYNAMIC:
return "PT_DYNAMIC";
break;
case PT_INTERP:
return "PT_INTERP";
break;
case PT_NOTE:
return "PT_NOTE";
break;
case PT_SHLIB:
return "PT_SHLIB";
break;
case PT_PHDR:
return "PT_PHDR";
break;
case PT_LOPROC:
return "PT_LOPROC/REGINFO";
break;
case PT_HIPROC:
return "PT_HIPROC";
break;
default:
return "PT_BOGUS";
break;
}
#endif
}
static void print_elfhdr(struct elfhdr *ehp)
{
int i;
printk("ELFHDR: e_ident<");
for(i = 0; i < (EI_NIDENT - 1); i++) printk("%x ", ehp->e_ident[i]);
printk("%x>\n", ehp->e_ident[i]);
printk(" e_type[%04x] e_machine[%04x] e_version[%08lx]\n",
pr_debug("ELFHDR: e_ident<");
for (i = 0; i < (EI_NIDENT - 1); i++)
pr_debug("%x ", ehp->e_ident[i]);
pr_debug("%x>\n", ehp->e_ident[i]);
pr_debug(" e_type[%04x] e_machine[%04x] e_version[%08lx]\n",
(unsigned short) ehp->e_type, (unsigned short) ehp->e_machine,
(unsigned long) ehp->e_version);
printk(" e_entry[%08lx] e_phoff[%08lx] e_shoff[%08lx] "
pr_debug(" e_entry[%08lx] e_phoff[%08lx] e_shoff[%08lx] "
"e_flags[%08lx]\n",
(unsigned long) ehp->e_entry, (unsigned long) ehp->e_phoff,
(unsigned long) ehp->e_shoff, (unsigned long) ehp->e_flags);
printk(" e_ehsize[%04x] e_phentsize[%04x] e_phnum[%04x]\n",
(unsigned short) ehp->e_ehsize, (unsigned short) ehp->e_phentsize,
pr_debug(" e_ehsize[%04x] e_phentsize[%04x] e_phnum[%04x]\n",
(unsigned short) ehp->e_ehsize,
(unsigned short) ehp->e_phentsize,
(unsigned short) ehp->e_phnum);
printk(" e_shentsize[%04x] e_shnum[%04x] e_shstrndx[%04x]\n",
(unsigned short) ehp->e_shentsize, (unsigned short) ehp->e_shnum,
pr_debug(" e_shentsize[%04x] e_shnum[%04x] e_shstrndx[%04x]\n",
(unsigned short) ehp->e_shentsize,
(unsigned short) ehp->e_shnum,
(unsigned short) ehp->e_shstrndx);
}
static void print_phdr(int i, struct elf_phdr *ep)
{
printk("PHDR[%d]: p_type[%s] p_offset[%08lx] p_vaddr[%08lx] "
pr_debug("PHDR[%d]: p_type[%s] p_offset[%08lx] p_vaddr[%08lx] "
"p_paddr[%08lx]\n", i, get_elf_p_type(ep->p_type),
(unsigned long) ep->p_offset, (unsigned long) ep->p_vaddr,
(unsigned long) ep->p_paddr);
printk(" p_filesz[%08lx] p_memsz[%08lx] p_flags[%08lx] "
pr_debug(" p_filesz[%08lx] p_memsz[%08lx] p_flags[%08lx] "
"p_align[%08lx]\n", (unsigned long) ep->p_filesz,
(unsigned long) ep->p_memsz, (unsigned long) ep->p_flags,
(unsigned long) ep->p_align);
......@@ -110,14 +141,13 @@ static void dump_phdrs(struct elf_phdr *ep, int pnum)
{
int i;
for(i = 0; i < pnum; i++, ep++) {
if((ep->p_type == PT_LOAD) ||
for (i = 0; i < pnum; i++, ep++) {
if ((ep->p_type == PT_LOAD) ||
(ep->p_type == PT_INTERP) ||
(ep->p_type == PT_PHDR))
print_phdr(i, ep);
}
}
#endif /* DEBUG */
static void set_brk(unsigned long start, unsigned long end)
{
......@@ -156,11 +186,10 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
elf_addr_t *envp;
elf_addr_t *sp, *csp;
#ifdef DEBUG
printk("create_irix_tables: p[%p] argc[%d] envc[%d] "
pr_debug("create_irix_tables: p[%p] argc[%d] envc[%d] "
"load_addr[%08x] interp_load_addr[%08x]\n",
p, argc, envc, load_addr, interp_load_addr);
#endif
sp = (elf_addr_t *) (~15UL & (unsigned long) p);
csp = sp;
csp -= exec ? DLINFO_ITEMS*2 : 2;
......@@ -181,7 +210,7 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
sp -= 2;
NEW_AUX_ENT(0, AT_NULL, 0);
if(exec) {
if (exec) {
sp -= 11*2;
NEW_AUX_ENT (0, AT_PHDR, load_addr + exec->e_phoff);
......@@ -245,9 +274,7 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
last_bss = 0;
error = load_addr = 0;
#ifdef DEBUG
print_elfhdr(interp_elf_ex);
#endif
/* First of all, some simple consistency checks */
if ((interp_elf_ex->e_type != ET_EXEC &&
......@@ -258,7 +285,7 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
}
/* Now read in all of the header information */
if(sizeof(struct elf_phdr) * interp_elf_ex->e_phnum > PAGE_SIZE) {
if (sizeof(struct elf_phdr) * interp_elf_ex->e_phnum > PAGE_SIZE) {
printk("IRIX interp header bigger than a page (%d)\n",
(sizeof(struct elf_phdr) * interp_elf_ex->e_phnum));
return 0xffffffff;
......@@ -267,7 +294,7 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
elf_phdata = kmalloc(sizeof(struct elf_phdr) * interp_elf_ex->e_phnum,
GFP_KERNEL);
if(!elf_phdata) {
if (!elf_phdata) {
printk("Cannot kmalloc phdata for IRIX interp.\n");
return 0xffffffff;
}
......@@ -275,7 +302,7 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
/* If the size of this structure has changed, then punt, since
* we will be doing the wrong thing.
*/
if(interp_elf_ex->e_phentsize != 32) {
if (interp_elf_ex->e_phentsize != 32) {
printk("IRIX interp e_phentsize == %d != 32 ",
interp_elf_ex->e_phentsize);
kfree(elf_phdata);
......@@ -286,27 +313,33 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
(char *) elf_phdata,
sizeof(struct elf_phdr) * interp_elf_ex->e_phnum);
#ifdef DEBUG
dump_phdrs(elf_phdata, interp_elf_ex->e_phnum);
#endif
eppnt = elf_phdata;
for(i=0; i<interp_elf_ex->e_phnum; i++, eppnt++) {
if(eppnt->p_type == PT_LOAD) {
for (i = 0; i < interp_elf_ex->e_phnum; i++, eppnt++) {
if (eppnt->p_type == PT_LOAD) {
int elf_type = MAP_PRIVATE | MAP_DENYWRITE;
int elf_prot = 0;
unsigned long vaddr = 0;
if (eppnt->p_flags & PF_R) elf_prot = PROT_READ;
if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE;
if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC;
if (eppnt->p_flags & PF_R)
elf_prot = PROT_READ;
if (eppnt->p_flags & PF_W)
elf_prot |= PROT_WRITE;
if (eppnt->p_flags & PF_X)
elf_prot |= PROT_EXEC;
elf_type |= MAP_FIXED;
vaddr = eppnt->p_vaddr;
pr_debug("INTERP do_mmap(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ",
pr_debug("INTERP do_mmap"
"(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ",
interpreter, vaddr,
(unsigned long) (eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)),
(unsigned long) elf_prot, (unsigned long) elf_type,
(unsigned long) (eppnt->p_offset & 0xfffff000));
(unsigned long)
(eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)),
(unsigned long)
elf_prot, (unsigned long) elf_type,
(unsigned long)
(eppnt->p_offset & 0xfffff000));
down_write(&current->mm->mmap_sem);
error = do_mmap(interpreter, vaddr,
eppnt->p_filesz + (eppnt->p_vaddr & 0xfff),
......@@ -314,33 +347,37 @@ static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex,
eppnt->p_offset & 0xfffff000);
up_write(&current->mm->mmap_sem);
if(error < 0 && error > -1024) {
printk("Aieee IRIX interp mmap error=%d\n", error);
if (error < 0 && error > -1024) {
printk("Aieee IRIX interp mmap error=%d\n",
error);
break; /* Real error */
}
pr_debug("error=%08lx ", (unsigned long) error);
if(!load_addr && interp_elf_ex->e_type == ET_DYN) {
if (!load_addr && interp_elf_ex->e_type == ET_DYN) {
load_addr = error;
pr_debug("load_addr = error ");
}
/* Find the end of the file mapping for this phdr, and keep
* track of the largest address we see for this.
/*
* Find the end of the file mapping for this phdr, and
* keep track of the largest address we see for this.
*/
k = eppnt->p_vaddr + eppnt->p_filesz;
if(k > elf_bss) elf_bss = k;
if (k > elf_bss)
elf_bss = k;
/* Do the same thing for the memory mapping - between
* elf_bss and last_bss is the bss section.
*/
k = eppnt->p_memsz + eppnt->p_vaddr;
if(k > last_bss) last_bss = k;
if (k > last_bss)
last_bss = k;
pr_debug("\n");
}
}
/* Now use mmap to map the library into memory. */
if(error < 0 && error > -1024) {
if (error < 0 && error > -1024) {
pr_debug("got error %d\n", error);
kfree(elf_phdata);
return 0xffffffff;
......@@ -377,7 +414,7 @@ static int verify_binary(struct elfhdr *ehp, struct linux_binprm *bprm)
return -ENOEXEC;
/* First of all, some simple consistency checks */
if((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) ||
if ((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) ||
!bprm->file->f_op->mmap) {
return -ENOEXEC;
}
......@@ -388,7 +425,7 @@ static int verify_binary(struct elfhdr *ehp, struct linux_binprm *bprm)
* XXX all registers as 64bits on cpu's capable of this at
* XXX exception time plus frob the XTLB exception vector.
*/
if((ehp->e_flags & EF_MIPS_ABI2))
if ((ehp->e_flags & EF_MIPS_ABI2))
return -ENOEXEC;
return 0;
......@@ -410,7 +447,7 @@ static inline int look_for_irix_interpreter(char **name,
struct file *file = NULL;
*name = NULL;
for(i = 0; i < pnum; i++, epp++) {
for (i = 0; i < pnum; i++, epp++) {
if (epp->p_type != PT_INTERP)
continue;
......@@ -467,8 +504,8 @@ static inline void map_executable(struct file *fp, struct elf_phdr *epp, int pnu
unsigned int tmp;
int i, prot;
for(i = 0; i < pnum; i++, epp++) {
if(epp->p_type != PT_LOAD)
for (i = 0; i < pnum; i++, epp++) {
if (epp->p_type != PT_LOAD)
continue;
/* Map it. */
......@@ -483,23 +520,23 @@ static inline void map_executable(struct file *fp, struct elf_phdr *epp, int pnu
up_write(&current->mm->mmap_sem);
/* Fixup location tracking vars. */
if((epp->p_vaddr & 0xfffff000) < *estack)
if ((epp->p_vaddr & 0xfffff000) < *estack)
*estack = (epp->p_vaddr & 0xfffff000);
if(!*laddr)
if (!*laddr)
*laddr = epp->p_vaddr - epp->p_offset;
if(epp->p_vaddr < *scode)
if (epp->p_vaddr < *scode)
*scode = epp->p_vaddr;
tmp = epp->p_vaddr + epp->p_filesz;
if(tmp > *ebss)
if (tmp > *ebss)
*ebss = tmp;
if((epp->p_flags & PF_X) && *ecode < tmp)
if ((epp->p_flags & PF_X) && *ecode < tmp)
*ecode = tmp;
if(*edata < tmp)
if (*edata < tmp)
*edata = tmp;
tmp = epp->p_vaddr + epp->p_memsz;
if(tmp > *ebrk)
if (tmp > *ebrk)
*ebrk = tmp;
}
......@@ -513,12 +550,12 @@ static inline int map_interpreter(struct elf_phdr *epp, struct elfhdr *ihp,
int i;
*eentry = 0xffffffff;
for(i = 0; i < pnum; i++, epp++) {
if(epp->p_type != PT_INTERP)
for (i = 0; i < pnum; i++, epp++) {
if (epp->p_type != PT_INTERP)
continue;
/* We should have fielded this error elsewhere... */
if(*eentry != 0xffffffff)
if (*eentry != 0xffffffff)
return -1;
set_fs(old_fs);
......@@ -604,9 +641,7 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
if (elf_ex.e_shnum > 20)
goto out;
#ifdef DEBUG
print_elfhdr(&elf_ex);
#endif
/* Now read in all of the header information */
size = elf_ex.e_phentsize * elf_ex.e_phnum;
......@@ -622,13 +657,11 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
if (retval < 0)
goto out_free_ph;
#ifdef DEBUG
dump_phdrs(elf_phdata, elf_ex.e_phnum);
#endif
/* Set some things for later. */
for(i = 0; i < elf_ex.e_phnum; i++) {
switch(elf_phdata[i].p_type) {
for (i = 0; i < elf_ex.e_phnum; i++) {
switch (elf_phdata[i].p_type) {
case PT_INTERP:
has_interp = 1;
elf_ihdr = &elf_phdata[i];
......@@ -667,7 +700,7 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
if (elf_interpreter) {
retval = verify_irix_interpreter(&interp_elf_ex);
if(retval)
if (retval)
goto out_free_interp;
}
......@@ -706,12 +739,12 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
&load_addr, &start_code, &elf_bss, &end_code,
&end_data, &elf_brk);
if(elf_interpreter) {
if (elf_interpreter) {
retval = map_interpreter(elf_phdata, &interp_elf_ex,
interpreter, &interp_load_addr,
elf_ex.e_phnum, old_fs, &elf_entry);
kfree(elf_interpreter);
if(retval) {
if (retval) {
set_fs(old_fs);
printk("Unable to load IRIX ELF interpreter\n");
send_sig(SIGSEGV, current, 0);
......@@ -809,12 +842,12 @@ static int load_irix_library(struct file *file)
return -ENOEXEC;
/* First of all, some simple consistency checks. */
if(elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 ||
if (elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 ||
!file->f_op->mmap)
return -ENOEXEC;
/* Now read in all of the header information. */
if(sizeof(struct elf_phdr) * elf_ex.e_phnum > PAGE_SIZE)
if (sizeof(struct elf_phdr) * elf_ex.e_phnum > PAGE_SIZE)
return -ENOEXEC;
elf_phdata = kmalloc(sizeof(struct elf_phdr) * elf_ex.e_phnum, GFP_KERNEL);
......@@ -825,15 +858,15 @@ static int load_irix_library(struct file *file)
sizeof(struct elf_phdr) * elf_ex.e_phnum);
j = 0;
for(i=0; i<elf_ex.e_phnum; i++)
if((elf_phdata + i)->p_type == PT_LOAD) j++;
for (i=0; i<elf_ex.e_phnum; i++)
if ((elf_phdata + i)->p_type == PT_LOAD) j++;
if(j != 1) {
if (j != 1) {
kfree(elf_phdata);
return -ENOEXEC;
}
while(elf_phdata->p_type != PT_LOAD) elf_phdata++;
while (elf_phdata->p_type != PT_LOAD) elf_phdata++;
/* Now use mmap to map the library into memory. */
down_write(&current->mm->mmap_sem);
......@@ -889,9 +922,7 @@ unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt)
return -EFAULT;
}
#ifdef DEBUG
dump_phdrs(user_phdrp, cnt);
#endif
for (i = 0; i < cnt; i++, hp++) {
if (__get_user(type, &hp->p_type))
......@@ -905,14 +936,14 @@ unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt)
filp = fget(fd);
if (!filp)
return -EACCES;
if(!filp->f_op) {
if (!filp->f_op) {
printk("irix_mapelf: Bogon filp!\n");
fput(filp);
return -EACCES;
}
hp = user_phdrp;
for(i = 0; i < cnt; i++, hp++) {
for (i = 0; i < cnt; i++, hp++) {
int prot;
retval = __get_user(vaddr, &hp->p_vaddr);
......@@ -1015,8 +1046,6 @@ static int notesize(struct memelfnote *en)
return sz;
}
/* #define DEBUG */
#define DUMP_WRITE(addr, nr) \
if (!dump_write(file, (addr), (nr))) \
goto end_coredump;
......@@ -1093,9 +1122,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
segs++;
}
#ifdef DEBUG
printk("irix_core_dump: %d segs taking %d bytes\n", segs, size);
#endif
pr_debug("irix_core_dump: %d segs taking %d bytes\n", segs, size);
/* Set up header. */
memcpy(elf.e_ident, ELFMAG, SELFMAG);
......@@ -1221,7 +1248,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
struct elf_phdr phdr;
int sz = 0;
for(i = 0; i < numnote; i++)
for (i = 0; i < numnote; i++)
sz += notesize(&notes[i]);
phdr.p_type = PT_NOTE;
......@@ -1241,7 +1268,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
dataoff = offset = roundup(offset, PAGE_SIZE);
/* Write program headers for segments dump. */
for(vma = current->mm->mmap, i = 0;
for (vma = current->mm->mmap, i = 0;
i < segs && vma != NULL; vma = vma->vm_next) {
struct elf_phdr phdr;
size_t sz;
......@@ -1267,7 +1294,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
DUMP_WRITE(&phdr, sizeof(phdr));
}
for(i = 0; i < numnote; i++)
for (i = 0; i < numnote; i++)
if (!writenote(&notes[i], file))
goto end_coredump;
......@@ -1275,7 +1302,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
DUMP_SEEK(dataoff);
for(i = 0, vma = current->mm->mmap;
for (i = 0, vma = current->mm->mmap;
i < segs && vma != NULL;
vma = vma->vm_next) {
unsigned long addr = vma->vm_start;
......@@ -1284,9 +1311,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
if (!maydump(vma))
continue;
i++;
#ifdef DEBUG
printk("elf_core_dump: writing %08lx %lx\n", addr, len);
#endif
pr_debug("elf_core_dump: writing %08lx %lx\n", addr, len);
DUMP_WRITE((void __user *)addr, len);
}
......
arch/mips/kernel/irq-msc01.c
View file @ e503606c
......@@ -112,7 +112,7 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
}
struct irq_chip msc_levelirq_type = {
.typename = "SOC-it-Level",
.name = "SOC-it-Level",
.ack = level_mask_and_ack_msc_irq,
.mask = mask_msc_irq,
.mask_ack = level_mask_and_ack_msc_irq,
......@@ -122,7 +122,7 @@ struct irq_chip msc_levelirq_type = {
};
struct irq_chip msc_edgeirq_type = {
.typename = "SOC-it-Edge",
.name = "SOC-it-Edge",
.ack = edge_mask_and_ack_msc_irq,
.mask = mask_msc_irq,
.mask_ack = edge_mask_and_ack_msc_irq,
......
arch/mips/kernel/irq-mv6434x.c
View file @ e503606c
......@@ -92,7 +92,7 @@ void ll_mv64340_irq(void)
}
struct irq_chip mv64340_irq_type = {
.typename = "MV-64340",
.name = "MV-64340",
.ack = mask_mv64340_irq,
.mask = mask_mv64340_irq,
.mask_ack = mask_mv64340_irq,
......
arch/mips/kernel/irq-rm7000.c
View file @ e503606c
......@@ -17,28 +17,27 @@
#include <asm/mipsregs.h>
#include <asm/system.h>
static int irq_base;
static inline void unmask_rm7k_irq(unsigned int irq)
{
set_c0_intcontrol(0x100 << (irq - irq_base));
set_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE));
}
static inline void mask_rm7k_irq(unsigned int irq)
{
clear_c0_intcontrol(0x100 << (irq - irq_base));
clear_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE));
}
static struct irq_chip rm7k_irq_controller = {
.typename = "RM7000",
.name = "RM7000",
.ack = mask_rm7k_irq,
.mask = mask_rm7k_irq,
.mask_ack = mask_rm7k_irq,
.unmask = unmask_rm7k_irq,
};
void __init rm7k_cpu_irq_init(int base)
void __init rm7k_cpu_irq_init(void)
{
int base = RM7K_CPU_IRQ_BASE;
int i;
clear_c0_intcontrol(0x00000f00); /* Mask all */
......@@ -46,6 +45,4 @@ void __init rm7k_cpu_irq_init(int base)
for (i = base; i < base + 4; i++)
set_irq_chip_and_handler(i, &rm7k_irq_controller,
handle_level_irq);
irq_base = base;
}
arch/mips/kernel/irq-rm9000.c
View file @ e503606c
......@@ -18,16 +18,14 @@
#include <asm/mipsregs.h>
#include <asm/system.h>
static int irq_base;
static inline void unmask_rm9k_irq(unsigned int irq)
{
set_c0_intcontrol(0x1000 << (irq - irq_base));
set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
}
static inline void mask_rm9k_irq(unsigned int irq)
{
clear_c0_intcontrol(0x1000 << (irq - irq_base));
clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
}
static inline void rm9k_cpu_irq_enable(unsigned int irq)
......@@ -39,15 +37,6 @@ static inline void rm9k_cpu_irq_enable(unsigned int irq)
local_irq_restore(flags);
}
static void rm9k_cpu_irq_disable(unsigned int irq)
{
unsigned long flags;
local_irq_save(flags);
mask_rm9k_irq(irq);
local_irq_restore(flags);
}
/*
* Performance counter interrupts are global on all processors.
*/
......@@ -81,7 +70,7 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq)
}
static struct irq_chip rm9k_irq_controller = {
.typename = "RM9000",
.name = "RM9000",
.ack = mask_rm9k_irq,
.mask = mask_rm9k_irq,
.mask_ack = mask_rm9k_irq,
......@@ -89,7 +78,7 @@ static struct irq_chip rm9k_irq_controller = {
};
static struct irq_chip rm9k_perfcounter_irq = {
.typename = "RM9000",
.name = "RM9000",
.startup = rm9k_perfcounter_irq_startup,
.shutdown = rm9k_perfcounter_irq_shutdown,
.ack = mask_rm9k_irq,
......@@ -102,8 +91,9 @@ unsigned int rm9000_perfcount_irq;
EXPORT_SYMBOL(rm9000_perfcount_irq);
void __init rm9k_cpu_irq_init(int base)
void __init rm9k_cpu_irq_init(void)
{
int base = RM9K_CPU_IRQ_BASE;
int i;
clear_c0_intcontrol(0x0000f000); /* Mask all */
......@@ -115,6 +105,4 @@ void __init rm9k_cpu_irq_init(int base)
rm9000_perfcount_irq = base + 1;
set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
handle_level_irq);
irq_base = base;
}
arch/mips/kernel/irq_cpu.c
View file @ e503606c
......@@ -25,7 +25,7 @@
* Don't even think about using this on SMP. You have been warned.
*
* This file exports one global function:
* void mips_cpu_irq_init(int irq_base);
* void mips_cpu_irq_init(void);
*/
#include <linux/init.h>
#include <linux/interrupt.h>
......@@ -36,22 +36,20 @@
#include <asm/mipsmtregs.h>
#include <asm/system.h>
static int mips_cpu_irq_base;
static inline void unmask_mips_irq(unsigned int irq)
{
set_c0_status(0x100 << (irq - mips_cpu_irq_base));
set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
irq_enable_hazard();
}
static inline void mask_mips_irq(unsigned int irq)
{
clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
irq_disable_hazard();
}
static struct irq_chip mips_cpu_irq_controller = {
.typename = "MIPS",
.name = "MIPS",
.ack = mask_mips_irq,
.mask = mask_mips_irq,
.mask_ack = mask_mips_irq,
......@@ -70,7 +68,7 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
{
unsigned int vpflags = dvpe();
clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags);
unmask_mips_mt_irq(irq);
......@@ -84,13 +82,13 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
static void mips_mt_cpu_irq_ack(unsigned int irq)
{
unsigned int vpflags = dvpe();
clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
evpe(vpflags);
mask_mips_mt_irq(irq);
}
static struct irq_chip mips_mt_cpu_irq_controller = {
.typename = "MIPS",
.name = "MIPS",
.startup = mips_mt_cpu_irq_startup,
.ack = mips_mt_cpu_irq_ack,
.mask = mask_mips_mt_irq,
......@@ -99,8 +97,9 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
.eoi = unmask_mips_mt_irq,
};
void __init mips_cpu_irq_init(int irq_base)
void __init mips_cpu_irq_init(void)
{
int irq_base = MIPS_CPU_IRQ_BASE;
int i;
/* Mask interrupts. */
......@@ -118,6 +117,4 @@ void __init mips_cpu_irq_init(int irq_base)
for (i = irq_base + 2; i < irq_base + 8; i++)
set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
handle_level_irq);
mips_cpu_irq_base = irq_base;
}
arch/mips/kernel/mips-mt.c
View file @ e503606c
......@@ -96,6 +96,10 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
goto out_unlock;
}
retval = security_task_setscheduler(p, 0, NULL);
if (retval)
goto out_unlock;
/* Record new user-specified CPU set for future reference */
p->thread.user_cpus_allowed = new_mask;
......@@ -141,8 +145,9 @@ asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
p = find_process_by_pid(pid);
if (!p)
goto out_unlock;
retval = 0;
retval = security_task_getscheduler(p);
if (retval)
goto out_unlock;
cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map);
......
arch/mips/kernel/process.c
View file @ e503606c
......@@ -41,10 +41,6 @@
#include <asm/isadep.h>
#include <asm/inst.h>
#include <asm/stacktrace.h>
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/mipsmtregs.h>
extern void smtc_idle_loop_hook(void);
#endif /* CONFIG_MIPS_MT_SMTC */
/*
* The idle thread. There's no useful work to be done, so just try to conserve
......@@ -57,6 +53,8 @@ ATTRIB_NORET void cpu_idle(void)
while (1) {
while (!need_resched()) {
#ifdef CONFIG_MIPS_MT_SMTC
extern void smtc_idle_loop_hook(void);
smtc_idle_loop_hook();
#endif /* CONFIG_MIPS_MT_SMTC */
if (cpu_wait)
......
arch/mips/kernel/r4k_fpu.S
View file @ e503606c
......@@ -114,6 +114,14 @@ LEAF(_save_fp_context32)
*/
LEAF(_restore_fp_context)
EX lw t0, SC_FPC_CSR(a0)
/* Fail if the CSR has exceptions pending */
srl t1, t0, 5
and t1, t0
andi t1, 0x1f << 7
bnez t1, fault
nop
#ifdef CONFIG_64BIT
EX ldc1 $f1, SC_FPREGS+8(a0)
EX ldc1 $f3, SC_FPREGS+24(a0)
......@@ -157,6 +165,14 @@ LEAF(_restore_fp_context)
LEAF(_restore_fp_context32)
/* Restore an o32 sigcontext. */
EX lw t0, SC32_FPC_CSR(a0)
/* Fail if the CSR has exceptions pending */
srl t1, t0, 5
and t1, t0
andi t1, 0x1f << 7
bnez t1, fault
nop
EX ldc1 $f0, SC32_FPREGS+0(a0)
EX ldc1 $f2, SC32_FPREGS+16(a0)
EX ldc1 $f4, SC32_FPREGS+32(a0)
......@@ -177,9 +193,10 @@ LEAF(_restore_fp_context32)
jr ra
li v0, 0 # success
END(_restore_fp_context32)
.set reorder
#endif
.set reorder
.type fault@function
.ent fault
fault: li v0, -EFAULT # failure
......
arch/mips/kernel/rtlx.c
View file @ e503606c
......@@ -63,7 +63,7 @@ extern void *vpe_get_shared(int index);
static void rtlx_dispatch(void)
{
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ);
do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);
}
......@@ -491,7 +491,7 @@ static struct irqaction rtlx_irq = {
.name = "RTLX",
};
static int rtlx_irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ;
static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;
static char register_chrdev_failed[] __initdata =
KERN_ERR "rtlx_module_init: unable to register device\n";
......
arch/mips/kernel/scall64-n32.S
View file @ e503606c
......@@ -384,7 +384,7 @@ EXPORT(sysn32_call_table)
PTR sys_readlinkat
PTR sys_fchmodat
PTR sys_faccessat
PTR sys_pselect6
PTR compat_sys_pselect6
PTR sys_ppoll /* 6265 */
PTR sys_unshare
PTR sys_splice
......
arch/mips/kernel/scall64-o32.S
View file @ e503606c
......@@ -506,7 +506,7 @@ sys_call_table:
PTR sys_readlinkat
PTR sys_fchmodat
PTR sys_faccessat /* 4300 */
PTR sys_pselect6
PTR compat_sys_pselect6
PTR sys_ppoll
PTR sys_unshare
PTR sys_splice
......
arch/mips/kernel/setup.c
View file @ e503606c
......@@ -271,8 +271,7 @@ static void __init bootmem_init(void)
static void __init bootmem_init(void)
{
unsigned long reserved_end;
unsigned long highest = 0;
unsigned long mapstart = -1UL;
unsigned long mapstart = ~0UL;
unsigned long bootmap_size;
int i;
......@@ -283,6 +282,13 @@ static void __init bootmem_init(void)
*/
reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end)));
/*
* max_low_pfn is not a number of pages. The number of pages
* of the system is given by 'max_low_pfn - min_low_pfn'.
*/
min_low_pfn = ~0UL;
max_low_pfn = 0;
/*
* Find the highest page frame number we have available.
*/
......@@ -296,8 +302,10 @@ static void __init bootmem_init(void)
end = PFN_DOWN(boot_mem_map.map[i].addr
+ boot_mem_map.map[i].size);
if (end > highest)
highest = end;
if (end > max_low_pfn)
max_low_pfn = end;
if (start < min_low_pfn)
min_low_pfn = start;
if (end <= reserved_end)
continue;
if (start >= mapstart)
......@@ -305,22 +313,36 @@ static void __init bootmem_init(void)
mapstart = max(reserved_end, start);
}
if (min_low_pfn >= max_low_pfn)
panic("Incorrect memory mapping !!!");
if (min_low_pfn > ARCH_PFN_OFFSET) {
printk(KERN_INFO
"Wasting %lu bytes for tracking %lu unused pages\n",
(min_low_pfn - ARCH_PFN_OFFSET) * sizeof(struct page),
min_low_pfn - ARCH_PFN_OFFSET);
} else if (min_low_pfn < ARCH_PFN_OFFSET) {
printk(KERN_INFO
"%lu free pages won't be used\n",
ARCH_PFN_OFFSET - min_low_pfn);
}
min_low_pfn = ARCH_PFN_OFFSET;
/*
* Determine low and high memory ranges
*/
if (highest > PFN_DOWN(HIGHMEM_START)) {
if (max_low_pfn > PFN_DOWN(HIGHMEM_START)) {
#ifdef CONFIG_HIGHMEM
highstart_pfn = PFN_DOWN(HIGHMEM_START);
highend_pfn = highest;
highend_pfn = max_low_pfn;
#endif
highest = PFN_DOWN(HIGHMEM_START);
max_low_pfn = PFN_DOWN(HIGHMEM_START);
}
/*
* Initialize the boot-time allocator with low memory only.
*/
bootmap_size = init_bootmem(mapstart, highest);
bootmap_size = init_bootmem_node(NODE_DATA(0), mapstart,
min_low_pfn, max_low_pfn);
/*
* Register fully available low RAM pages with the bootmem allocator.
*/
......@@ -541,3 +563,6 @@ int __init dsp_disable(char *s)
}
__setup("nodsp", dsp_disable);
unsigned long kernelsp[NR_CPUS];
unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
arch/mips/kernel/smp-mt.c
View file @ e503606c
......@@ -35,7 +35,6 @@
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>
#include <asm/mips-boards/maltaint.h> /* This is f*cking wrong */
#define MIPS_CPU_IPI_RESCHED_IRQ 0
#define MIPS_CPU_IPI_CALL_IRQ 1
......@@ -108,12 +107,12 @@ void __init sanitize_tlb_entries(void)
static void ipi_resched_dispatch(void)
{
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}
static void ipi_call_dispatch(void)
{
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ);
do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
......@@ -270,8 +269,8 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
}
cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
setup_irq(cpu_ipi_resched_irq, &irq_resched);
setup_irq(cpu_ipi_call_irq, &irq_call);
......
arch/mips/kernel/smtc.c
View file @ e503606c
......@@ -26,16 +26,6 @@
* This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
*/
/*
* MIPSCPU_INT_BASE is identically defined in both
* asm-mips/mips-boards/maltaint.h and asm-mips/mips-boards/simint.h,
* but as yet there's no properly organized include structure that
* will ensure that the right *int.h file will be included for a
* given platform build.
*/
#define MIPSCPU_INT_BASE 16
#define MIPS_CPU_IPI_IRQ 1
#define LOCK_MT_PRA() \
......@@ -77,15 +67,15 @@ unsigned int ipi_timer_latch[NR_CPUS];
#define IPIBUF_PER_CPU 4
struct smtc_ipi_q IPIQ[NR_CPUS];
struct smtc_ipi_q freeIPIq;
static struct smtc_ipi_q IPIQ[NR_CPUS];
static struct smtc_ipi_q freeIPIq;
/* Forward declarations */
void ipi_decode(struct smtc_ipi *);
void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
void setup_cross_vpe_interrupts(void);
static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
static void setup_cross_vpe_interrupts(void);
void init_smtc_stats(void);
/* Global SMTC Status */
......@@ -200,7 +190,7 @@ void __init sanitize_tlb_entries(void)
* Configure shared TLB - VPC configuration bit must be set by caller
*/
void smtc_configure_tlb(void)
static void smtc_configure_tlb(void)
{
int i,tlbsiz,vpes;
unsigned long mvpconf0;
......@@ -648,7 +638,7 @@ int setup_irq_smtc(unsigned int irq, struct irqaction * new,
* the VPE.
*/
void smtc_ipi_qdump(void)
static void smtc_ipi_qdump(void)
{
int i;
......@@ -686,28 +676,6 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
return result;
}
/* No longer used in IPI dispatch, but retained for future recycling */
static __inline__ int atomic_postclear(unsigned int *pv)
{
unsigned long result;
unsigned long temp;
__asm__ __volatile__(
"1: ll %0, %2 \n"
" or %1, $0, $0 \n"
" sc %1, %2 \n"
" beqz %1, 1b \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (*pv)
: "m" (*pv)
: "memory");
return result;
}
void smtc_send_ipi(int cpu, int type, unsigned int action)
{
int tcstatus;
......@@ -781,7 +749,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
/*
* Send IPI message to Halted TC, TargTC/TargVPE already having been set
*/
void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
{
struct pt_regs *kstack;
unsigned long tcstatus;
......@@ -921,7 +889,7 @@ void smtc_timer_broadcast(int vpe)
* interrupts.
*/
static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ;
static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
{
......@@ -1000,7 +968,7 @@ static void ipi_irq_dispatch(void)
static struct irqaction irq_ipi;
void setup_cross_vpe_interrupts(void)
static void setup_cross_vpe_interrupts(void)
{
if (!cpu_has_vint)
panic("SMTC Kernel requires Vectored Interupt support");
......@@ -1296,7 +1264,7 @@ void smtc_flush_tlb_asid(unsigned long asid)
* Support for single-threading cache flush operations.
*/
int halt_state_save[NR_CPUS];
static int halt_state_save[NR_CPUS];
/*
* To really, really be sure that nothing is being done
......
arch/mips/kernel/vpe.c
View file @ e503606c
......@@ -695,7 +695,7 @@ static void dump_tclist(void)
}
/* We are prepared so configure and start the VPE... */
int vpe_run(struct vpe * v)
static int vpe_run(struct vpe * v)
{
struct vpe_notifications *n;
unsigned long val, dmt_flag;
......@@ -832,7 +832,7 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
* contents of the program (p)buffer performing relocatations/etc, free's it
* when finished.
*/
int vpe_elfload(struct vpe * v)
static int vpe_elfload(struct vpe * v)
{
Elf_Ehdr *hdr;
Elf_Shdr *sechdrs;
......
arch/mips/lasat/interrupt.c
View file @ e503606c
......@@ -45,7 +45,7 @@ void enable_lasat_irq(unsigned int irq_nr)
}
static struct irq_chip lasat_irq_type = {
.typename = "Lasat",
.name = "Lasat",
.ack = disable_lasat_irq,
.mask = disable_lasat_irq,
.mask_ack = disable_lasat_irq,
......
arch/mips/lasat/prom.c
View file @ e503606c
......@@ -132,9 +132,8 @@ void __init prom_init(void)
add_memory_region(0, lasat_board_info.li_memsize, BOOT_MEM_RAM);
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
const char *get_system_type(void)
......
arch/mips/lib-32/Makefile
View file @ e503606c
......@@ -2,7 +2,7 @@
# Makefile for MIPS-specific library files..
#
lib-y += memset.o watch.o
lib-y += watch.o
obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
......
arch/mips/lib-64/Makefile
View file @ e503606c
......@@ -2,7 +2,7 @@
# Makefile for MIPS-specific library files..
#
lib-y += memset.o watch.o
lib-y += watch.o
obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
......
arch/mips/lib-64/memset.S deleted 100644 → 0
View file @ 76c32956
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 1999, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/regdef.h>
#define EX(insn,reg,addr,handler) \
9: insn reg, addr; \
.section __ex_table,"a"; \
PTR 9b, handler; \
.previous
.macro f_fill64 dst, offset, val, fixup
EX(LONG_S, \val, (\offset + 0 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 1 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 2 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 3 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 4 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 5 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 6 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 7 * LONGSIZE)(\dst), \fixup)
.endm
/*
* memset(void *s, int c, size_t n)
*
* a0: start of area to clear
* a1: char to fill with
* a2: size of area to clear
*/
.set noreorder
.align 5
LEAF(memset)
beqz a1, 1f
move v0, a0 /* result */
andi a1, 0xff /* spread fillword */
dsll t1, a1, 8
or a1, t1
dsll t1, a1, 16
or a1, t1
dsll t1, a1, 32
or a1, t1
1:
FEXPORT(__bzero)
sltiu t0, a2, LONGSIZE /* very small region? */
bnez t0, small_memset
andi t0, a0, LONGMASK /* aligned? */
beqz t0, 1f
PTR_SUBU t0, LONGSIZE /* alignment in bytes */
#ifdef __MIPSEB__
EX(sdl, a1, (a0), first_fixup) /* make dword aligned */
#endif
#ifdef __MIPSEL__
EX(sdr, a1, (a0), first_fixup) /* make dword aligned */
#endif
PTR_SUBU a0, t0 /* long align ptr */
PTR_ADDU a2, t0 /* correct size */
1: ori t1, a2, 0x3f /* # of full blocks */
xori t1, 0x3f
beqz t1, memset_partial /* no block to fill */
andi t0, a2, 0x38
PTR_ADDU t1, a0 /* end address */
.set reorder
1: PTR_ADDIU a0, 64
f_fill64 a0, -64, a1, fwd_fixup
bne t1, a0, 1b
.set noreorder
memset_partial:
PTR_LA t1, 2f /* where to start */
.set noat
dsrl AT, t0, 1
PTR_SUBU t1, AT
.set noat
jr t1
PTR_ADDU a0, t0 /* dest ptr */
.set push
.set noreorder
.set nomacro
f_fill64 a0, -64, a1, partial_fixup /* ... but first do longs ... */
2: .set pop
andi a2, LONGMASK /* At most one long to go */
beqz a2, 1f
PTR_ADDU a0, a2 /* What's left */
#ifdef __MIPSEB__
EX(sdr, a1, -1(a0), last_fixup)
#endif
#ifdef __MIPSEL__
EX(sdl, a1, -1(a0), last_fixup)
#endif
1: jr ra
move a2, zero
small_memset:
beqz a2, 2f
PTR_ADDU t1, a0, a2
1: PTR_ADDIU a0, 1 /* fill bytewise */
bne t1, a0, 1b
sb a1, -1(a0)
2: jr ra /* done */
move a2, zero
END(memset)
first_fixup:
jr ra
nop
fwd_fixup:
PTR_L t0, TI_TASK($28)
LONG_L t0, THREAD_BUADDR(t0)
andi a2, 0x3f
LONG_ADDU a2, t1
jr ra
LONG_SUBU a2, t0
partial_fixup:
PTR_L t0, TI_TASK($28)
LONG_L t0, THREAD_BUADDR(t0)
andi a2, LONGMASK
LONG_ADDU a2, t1
jr ra
LONG_SUBU a2, t0
last_fixup:
jr ra
andi v1, a2, LONGMASK
arch/mips/lib/Makefile
View file @ e503606c
......@@ -2,7 +2,7 @@
# Makefile for MIPS-specific library files..
#
lib-y += csum_partial.o memcpy.o promlib.o \
lib-y += csum_partial.o memcpy.o memset.o promlib.o \
strlen_user.o strncpy_user.o strnlen_user.o uncached.o
obj-y += iomap.o
......
arch/mips/lib-32/memset.S → arch/mips/lib/memset.S
View file @ e503606c
......@@ -10,6 +10,14 @@
#include <asm/asm-offsets.h>
#include <asm/regdef.h>
#if LONGSIZE == 4
#define LONG_S_L swl
#define LONG_S_R swr
#else
#define LONG_S_L sdl
#define LONG_S_R sdr
#endif
#define EX(insn,reg,addr,handler) \
9: insn reg, addr; \
.section __ex_table,"a"; \
......@@ -25,6 +33,7 @@
EX(LONG_S, \val, (\offset + 5 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 6 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 7 * LONGSIZE)(\dst), \fixup)
#if LONGSIZE == 4
EX(LONG_S, \val, (\offset + 8 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 9 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 10 * LONGSIZE)(\dst), \fixup)
......@@ -33,6 +42,7 @@
EX(LONG_S, \val, (\offset + 13 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 14 * LONGSIZE)(\dst), \fixup)
EX(LONG_S, \val, (\offset + 15 * LONGSIZE)(\dst), \fixup)
#endif
.endm
/*
......@@ -49,9 +59,13 @@ LEAF(memset)
move v0, a0 /* result */
andi a1, 0xff /* spread fillword */
sll t1, a1, 8
LONG_SLL t1, a1, 8
or a1, t1
sll t1, a1, 16
LONG_SLL t1, a1, 16
#if LONGSIZE == 8
or a1, t1
LONG_SLL t1, a1, 32
#endif
or a1, t1
1:
......@@ -64,10 +78,10 @@ FEXPORT(__bzero)
PTR_SUBU t0, LONGSIZE /* alignment in bytes */
#ifdef __MIPSEB__
EX(swl, a1, (a0), first_fixup) /* make word aligned */
EX(LONG_S_L, a1, (a0), first_fixup) /* make word/dword aligned */
#endif
#ifdef __MIPSEL__
EX(swr, a1, (a0), first_fixup) /* make word aligned */
EX(LONG_S_R, a1, (a0), first_fixup) /* make word/dword aligned */
#endif
PTR_SUBU a0, t0 /* long align ptr */
PTR_ADDU a2, t0 /* correct size */
......@@ -75,7 +89,7 @@ FEXPORT(__bzero)
1: ori t1, a2, 0x3f /* # of full blocks */
xori t1, 0x3f
beqz t1, memset_partial /* no block to fill */
andi t0, a2, 0x3c
andi t0, a2, 0x40-LONGSIZE
PTR_ADDU t1, a0 /* end address */
.set reorder
......@@ -86,7 +100,14 @@ FEXPORT(__bzero)
memset_partial:
PTR_LA t1, 2f /* where to start */
#if LONGSIZE == 4
PTR_SUBU t1, t0
#else
.set noat
LONG_SRL AT, t0, 1
PTR_SUBU t1, AT
.set noat
#endif
jr t1
PTR_ADDU a0, t0 /* dest ptr */
......@@ -100,10 +121,10 @@ memset_partial:
beqz a2, 1f
PTR_ADDU a0, a2 /* What's left */
#ifdef __MIPSEB__
EX(swr, a1, -1(a0), last_fixup)
EX(LONG_S_R, a1, -1(a0), last_fixup)
#endif
#ifdef __MIPSEL__
EX(swl, a1, -1(a0), last_fixup)
EX(LONG_S_L, a1, -1(a0), last_fixup)
#endif
1: jr ra
move a2, zero
......
arch/mips/lib/uncached.c
View file @ e503606c
......@@ -44,20 +44,24 @@ unsigned long __init run_uncached(void *func)
if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
usp = CKSEG1ADDR(sp);
#ifdef CONFIG_64BIT
else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) &&
(long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0))
usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
XKPHYS_TO_PHYS((long long)sp));
#endif
else {
BUG();
usp = sp;
}
if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
ufunc = CKSEG1ADDR(lfunc);
#ifdef CONFIG_64BIT
else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0LL, 0) &&
(long long)lfunc < (long long)PHYS_TO_XKPHYS(8LL, 0))
ufunc = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
XKPHYS_TO_PHYS((long long)lfunc));
#endif
else {
BUG();
ufunc = lfunc;
......
arch/mips/mips-boards/atlas/atlas_int.c
View file @ e503606c
......@@ -32,6 +32,7 @@
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/kernel.h>
#include <asm/gdb-stub.h>
#include <asm/io.h>
......@@ -69,7 +70,7 @@ static void end_atlas_irq(unsigned int irq)
}
static struct irq_chip atlas_irq_type = {
.typename = "Atlas",
.name = "Atlas",
.ack = disable_atlas_irq,
.mask = disable_atlas_irq,
.mask_ack = disable_atlas_irq,
......@@ -220,7 +221,7 @@ msc_irqmap_t __initdata msc_irqmap[] = {
{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
};
int __initdata msc_nr_irqs = sizeof(msc_irqmap) / sizeof(*msc_irqmap);
int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
msc_irqmap_t __initdata msc_eicirqmap[] = {
{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
......@@ -231,14 +232,14 @@ msc_irqmap_t __initdata msc_eicirqmap[] = {
{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
};
int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap) / sizeof(*msc_eicirqmap);
int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
void __init arch_init_irq(void)
{
init_atlas_irqs(ATLAS_INT_BASE);
if (!cpu_has_veic)
mips_cpu_irq_init(MIPSCPU_INT_BASE);
mips_cpu_irq_init();
switch(mips_revision_corid) {
case MIPS_REVISION_CORID_CORE_MSC:
......
arch/mips/mips-boards/generic/memory.c
View file @ e503606c
......@@ -166,9 +166,8 @@ void __init prom_meminit(void)
}
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
unsigned long freed = 0;
unsigned long addr;
int i;
......@@ -176,17 +175,8 @@ unsigned long __init prom_free_prom_memory(void)
if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
continue;
addr = PAGE_ALIGN(boot_mem_map.map[i].addr);
while (addr < boot_mem_map.map[i].addr
+ boot_mem_map.map[i].size) {
ClearPageReserved(virt_to_page(__va(addr)));
init_page_count(virt_to_page(__va(addr)));
free_page((unsigned long)__va(addr));
addr += PAGE_SIZE;
freed += PAGE_SIZE;
addr = boot_mem_map.map[i].addr;
free_init_pages("prom memory",
addr, addr + boot_mem_map.map[i].size);
}
}
printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
return freed;
}
arch/mips/mips-boards/malta/malta_int.c
View file @ e503606c
......@@ -27,6 +27,7 @@
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/kernel.h>
#include <linux/random.h>
#include <asm/i8259.h>
......@@ -289,7 +290,7 @@ msc_irqmap_t __initdata msc_irqmap[] = {
{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
};
int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
msc_irqmap_t __initdata msc_eicirqmap[] = {
{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
......@@ -303,14 +304,14 @@ msc_irqmap_t __initdata msc_eicirqmap[] = {
{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
};
int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
void __init arch_init_irq(void)
{
init_i8259_irqs();
if (!cpu_has_veic)
mips_cpu_irq_init (MIPSCPU_INT_BASE);
mips_cpu_irq_init();
switch(mips_revision_corid) {
case MIPS_REVISION_CORID_CORE_MSC:
......
arch/mips/mips-boards/sead/sead_int.c
View file @ e503606c
......@@ -113,5 +113,5 @@ asmlinkage void plat_irq_dispatch(void)
void __init arch_init_irq(void)
{
mips_cpu_irq_init(MIPSCPU_INT_BASE);
mips_cpu_irq_init();
}
arch/mips/mips-boards/sim/sim_int.c
View file @ e503606c
......@@ -21,9 +21,7 @@
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/mips-boards/simint.h>
extern void mips_cpu_irq_init(int);
#include <asm/irq_cpu.h>
static inline int clz(unsigned long x)
{
......@@ -86,5 +84,5 @@ asmlinkage void plat_irq_dispatch(void)
void __init arch_init_irq(void)
{
mips_cpu_irq_init(MIPSCPU_INT_BASE);
mips_cpu_irq_init();
}
arch/mips/mips-boards/sim/sim_mem.c
View file @ e503606c
......@@ -99,10 +99,9 @@ void __init prom_meminit(void)
}
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
int i;
unsigned long freed = 0;
unsigned long addr;
for (i = 0; i < boot_mem_map.nr_map; i++) {
......@@ -110,16 +109,7 @@ unsigned long __init prom_free_prom_memory(void)
continue;
addr = boot_mem_map.map[i].addr;
while (addr < boot_mem_map.map[i].addr
+ boot_mem_map.map[i].size) {
ClearPageReserved(virt_to_page(__va(addr)));
init_page_count(virt_to_page(__va(addr)));
free_page((unsigned long)__va(addr));
addr += PAGE_SIZE;
freed += PAGE_SIZE;
free_init_pages("prom memory",
addr, addr + boot_mem_map.map[i].size);
}
}
printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
return freed;
}
arch/mips/mm/init.c
View file @ e503606c
......@@ -341,7 +341,6 @@ static int __init page_is_ram(unsigned long pagenr)
void __init paging_init(void)
{
unsigned long zones_size[MAX_NR_ZONES] = { 0, };
unsigned long max_dma, low;
#ifndef CONFIG_FLATMEM
unsigned long zholes_size[MAX_NR_ZONES] = { 0, };
unsigned long i, j, pfn;
......@@ -354,19 +353,19 @@ void __init paging_init(void)
#endif
kmap_coherent_init();
max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
low = max_low_pfn;
#ifdef CONFIG_ISA
if (low < max_dma)
zones_size[ZONE_DMA] = low;
else {
zones_size[ZONE_DMA] = max_dma;
zones_size[ZONE_NORMAL] = low - max_dma;
if (max_low_pfn >= MAX_DMA_PFN)
if (min_low_pfn >= MAX_DMA_PFN) {
zones_size[ZONE_DMA] = 0;
zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
} else {
zones_size[ZONE_DMA] = MAX_DMA_PFN - min_low_pfn;
zones_size[ZONE_NORMAL] = max_low_pfn - MAX_DMA_PFN;
}
#else
zones_size[ZONE_DMA] = low;
else
#endif
zones_size[ZONE_DMA] = max_low_pfn - min_low_pfn;
#ifdef CONFIG_HIGHMEM
zones_size[ZONE_HIGHMEM] = highend_pfn - highstart_pfn;
......@@ -467,7 +466,7 @@ void __init mem_init(void)
}
#endif /* !CONFIG_NEED_MULTIPLE_NODES */
static void free_init_pages(char *what, unsigned long begin, unsigned long end)
void free_init_pages(const char *what, unsigned long begin, unsigned long end)
{
unsigned long pfn;
......@@ -493,18 +492,25 @@ void free_initrd_mem(unsigned long start, unsigned long end)
}
#endif
extern unsigned long prom_free_prom_memory(void);
void free_initmem(void)
{
unsigned long freed;
freed = prom_free_prom_memory();
if (freed)
printk(KERN_INFO "Freeing firmware memory: %ldkb freed\n",
freed >> 10);
prom_free_prom_memory();
free_init_pages("unused kernel memory",
__pa_symbol(&__init_begin),
__pa_symbol(&__init_end));
}
unsigned long pgd_current[NR_CPUS];
/*
* On 64-bit we've got three-level pagetables with a slightly
* different layout ...
*/
#define __page_aligned(order) __attribute__((__aligned__(PAGE_SIZE<<order)))
pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned(PGD_ORDER);
#ifdef CONFIG_64BIT
#ifdef MODULE_START
pgd_t module_pg_dir[PTRS_PER_PGD] __page_aligned(PGD_ORDER);
#endif
pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned(PMD_ORDER);
#endif
pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER);
arch/mips/momentum/jaguar_atx/Makefile
View file @ e503606c
......@@ -6,7 +6,7 @@
# unless it's something special (ie not a .c file).
#
obj-y += irq.o prom.o reset.o setup.o
obj-y += irq.o platform.o prom.o reset.o setup.o
obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
arch/mips/momentum/jaguar_atx/irq.c
View file @ e503606c
......@@ -82,8 +82,8 @@ void __init arch_init_irq(void)
*/
clear_c0_status(ST0_IM);
mips_cpu_irq_init(0);
rm7k_cpu_irq_init(8);
mips_cpu_irq_init();
rm7k_cpu_irq_init();
/* set up the cascading interrupts */
setup_irq(8, &cascade_mv64340);
......
arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h
View file @ e503606c
......@@ -46,7 +46,9 @@
extern unsigned long ja_fpga_base;
#define JAGUAR_FPGA_WRITE(x,y) writeb(x, ja_fpga_base + JAGUAR_ATX_REG_##y)
#define JAGUAR_FPGA_READ(x) readb(ja_fpga_base + JAGUAR_ATX_REG_##x)
#define __FPGA_REG_TO_ADDR(reg) \
((void *) ja_fpga_base + JAGUAR_ATX_REG_##reg)
#define JAGUAR_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
#define JAGUAR_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
#endif
arch/mips/momentum/jaguar_atx/platform.c 0 → 100644
View file @ e503606c
#include <linux/delay.h>
#include <linux/if_ether.h>
#include <linux/ioport.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
#include "jaguar_atx_fpga.h"
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
.name = "ethernet shared base",
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
MV643XX_ETH_SHARED_REGS_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv643xx_eth_shared_device = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
.resource = mv643xx_eth_shared_resources,
};
#define MV_SRAM_BASE 0xfe000000UL
#define MV_SRAM_SIZE (256 * 1024)
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
#define MV64x60_IRQ_ETH_0 48
#define MV64x60_IRQ_ETH_1 49
#define MV64x60_IRQ_ETH_2 50
#ifdef CONFIG_MV643XX_ETH_0
static struct resource mv64x60_eth0_resources[] = {
[0] = {
.name = "eth0 irq",
.start = MV64x60_IRQ_ETH_0,
.end = MV64x60_IRQ_ETH_0,
.flags = IORESOURCE_IRQ,
},
};
static char eth0_mac_addr[ETH_ALEN];
static struct mv643xx_eth_platform_data eth0_pd = {
.mac_addr = eth0_mac_addr,
.tx_sram_addr = MV_SRAM_BASE_ETH0,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
.resource = mv64x60_eth0_resources,
.dev = {
.platform_data = &eth0_pd,
},
};
#endif /* CONFIG_MV643XX_ETH_0 */
#ifdef CONFIG_MV643XX_ETH_1
static struct resource mv64x60_eth1_resources[] = {
[0] = {
.name = "eth1 irq",
.start = MV64x60_IRQ_ETH_1,
.end = MV64x60_IRQ_ETH_1,
.flags = IORESOURCE_IRQ,
},
};
static char eth1_mac_addr[ETH_ALEN];
static struct mv643xx_eth_platform_data eth1_pd = {
.mac_addr = eth1_mac_addr,
.tx_sram_addr = MV_SRAM_BASE_ETH1,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
.resource = mv64x60_eth1_resources,
.dev = {
.platform_data = &eth1_pd,
},
};
#endif /* CONFIG_MV643XX_ETH_1 */
#ifdef CONFIG_MV643XX_ETH_2
static struct resource mv64x60_eth2_resources[] = {
[0] = {
.name = "eth2 irq",
.start = MV64x60_IRQ_ETH_2,
.end = MV64x60_IRQ_ETH_2,
.flags = IORESOURCE_IRQ,
},
};
static char eth2_mac_addr[ETH_ALEN];
static struct mv643xx_eth_platform_data eth2_pd = {
.mac_addr = eth2_mac_addr,
};
static struct platform_device eth2_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
.resource = mv64x60_eth2_resources,
.dev = {
.platform_data = &eth2_pd,
},
};
#endif /* CONFIG_MV643XX_ETH_2 */
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
&mv643xx_eth_shared_device,
#ifdef CONFIG_MV643XX_ETH_0
&eth0_device,
#endif
#ifdef CONFIG_MV643XX_ETH_1
&eth1_device,
#endif
#ifdef CONFIG_MV643XX_ETH_2
&eth2_device,
#endif
};
static u8 __init exchange_bit(u8 val, u8 cs)
{
/* place the data */
JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
udelay(1);
/* turn the clock on */
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
udelay(1);
/* turn the clock off and read-strobe */
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return (JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
}
static void __init get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
/*
* Copy and increment ethernet MAC address by a small value.
*
* This is useful for systems where the only one MAC address is stored in
* non-volatile memory for multiple ports.
*/
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
unsigned int add)
{
int i;
BUG_ON(add >= 256);
for (i = ETH_ALEN; i >= 0; i--) {
dst[i] = src[i] + add;
add = dst[i] < src[i]; /* compute carry */
}
WARN_ON(add);
}
static int __init mv643xx_eth_add_pds(void)
{
unsigned char mac[ETH_ALEN];
int ret;
get_mac(mac);
#ifdef CONFIG_MV643XX_ETH_0
eth_mac_add(eth1_mac_addr, mac, 0);
#endif
#ifdef CONFIG_MV643XX_ETH_1
eth_mac_add(eth1_mac_addr, mac, 1);
#endif
#ifdef CONFIG_MV643XX_ETH_2
eth_mac_add(eth2_mac_addr, mac, 2);
#endif
ret = platform_add_devices(mv643xx_eth_pd_devs,
ARRAY_SIZE(mv643xx_eth_pd_devs));
return ret;
}
device_initcall(mv643xx_eth_add_pds);
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
arch/mips/momentum/jaguar_atx/prom.c
View file @ e503606c
......@@ -39,56 +39,6 @@ const char *get_system_type(void)
return "Momentum Jaguar-ATX";
}
#ifdef CONFIG_MV643XX_ETH
extern unsigned char prom_mac_addr_base[6];
static void burn_clocks(void)
{
int i;
/* this loop should burn at least 1us -- this should be plenty */
for (i = 0; i < 0x10000; i++)
;
}
static u8 exchange_bit(u8 val, u8 cs)
{
/* place the data */
JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
burn_clocks();
/* turn the clock on */
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
burn_clocks();
/* turn the clock off and read-strobe */
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
}
void get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
#endif
#ifdef CONFIG_64BIT
unsigned long signext(unsigned long addr)
......@@ -228,16 +178,10 @@ void __init prom_init(void)
#endif /* CONFIG_64BIT */
mips_machgroup = MACH_GROUP_MOMENCO;
mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
#ifdef CONFIG_MV643XX_ETH
/* get the base MAC address for on-board ethernet ports */
get_mac(prom_mac_addr_base);
#endif
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
......
arch/mips/momentum/ocelot_3/irq.c
View file @ e503606c
......@@ -65,7 +65,7 @@ void __init arch_init_irq(void)
*/
clear_c0_status(ST0_IM | ST0_BEV);
rm7k_cpu_irq_init(8);
rm7k_cpu_irq_init();
/* set up the cascading interrupts */
setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */
......
arch/mips/momentum/ocelot_3/prom.c
View file @ e503606c
......@@ -180,9 +180,8 @@ void __init prom_init(void)
#endif
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
......
arch/mips/momentum/ocelot_c/cpci-irq.c
View file @ e503606c
......@@ -84,7 +84,7 @@ void ll_cpci_irq(void)
}
struct irq_chip cpci_irq_type = {
.typename = "CPCI/FPGA",
.name = "CPCI/FPGA",
.ack = mask_cpci_irq,
.mask = mask_cpci_irq,
.mask_ack = mask_cpci_irq,
......
arch/mips/momentum/ocelot_c/dbg_io.c
View file @ e503606c
#ifdef CONFIG_KGDB
#include <asm/serial.h> /* For the serial port location and base baud */
/* --- CONFIG --- */
......@@ -121,5 +119,3 @@ int putDebugChar(uint8 byte)
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
arch/mips/momentum/ocelot_c/irq.c
View file @ e503606c
......@@ -94,7 +94,7 @@ void __init arch_init_irq(void)
*/
clear_c0_status(ST0_IM);
mips_cpu_irq_init(0);
mips_cpu_irq_init();
/* set up the cascading interrupts */
setup_irq(3, &cascade_fpga);
......
arch/mips/momentum/ocelot_c/prom.c
View file @ e503606c
......@@ -178,7 +178,6 @@ void __init prom_init(void)
#endif
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
arch/mips/momentum/ocelot_c/uart-irq.c
View file @ e503606c
......@@ -77,7 +77,7 @@ void ll_uart_irq(void)
}
struct irq_chip uart_irq_type = {
.typename = "UART/FPGA",
.name = "UART/FPGA",
.ack = mask_uart_irq,
.mask = mask_uart_irq,
.mask_ack = mask_uart_irq,
......
arch/mips/momentum/ocelot_g/dbg_io.c
View file @ e503606c
#ifdef CONFIG_KGDB
#include <asm/serial.h> /* For the serial port location and base baud */
/* --- CONFIG --- */
......@@ -121,5 +119,3 @@ int putDebugChar(uint8 byte)
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
arch/mips/momentum/ocelot_g/irq.c
View file @ e503606c
......@@ -94,8 +94,8 @@ void __init arch_init_irq(void)
clear_c0_status(ST0_IM);
local_irq_disable();
mips_cpu_irq_init(0);
rm7k_cpu_irq_init(8);
mips_cpu_irq_init();
rm7k_cpu_irq_init();
gt64240_irq_init();
}
arch/mips/momentum/ocelot_g/prom.c
View file @ e503606c
......@@ -79,7 +79,6 @@ void __init prom_init(void)
}
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
arch/mips/oprofile/Kconfig
View file @ e503606c
......@@ -11,7 +11,7 @@ config PROFILING
config OPROFILE
tristate "OProfile system profiling (EXPERIMENTAL)"
depends on PROFILING && EXPERIMENTAL
depends on PROFILING && !!MIPS_MT_SMTC && EXPERIMENTAL
help
OProfile is a profiling system capable of profiling the
whole system, include the kernel, kernel modules, libraries,
......
arch/mips/pci/fixup-vr4133.c
View file @ e503606c
......@@ -17,8 +17,10 @@
*/
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <asm/i8259.h>
#include <asm/vr41xx/cmbvr4133.h>
extern int vr4133_rockhopper;
......@@ -142,7 +144,7 @@ int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot)
if (bus == NULL)
return -1;
for (i = 0; i < sizeof (int_map) / sizeof (int_map[0]); i++) {
for (i = 0; i < ARRAY_SIZE(int_map); i++) {
if (int_map[i].bus == bus->number && int_map[i].slot == slot) {
int line;
for (line = 0; line < 4; line++)
......@@ -160,17 +162,7 @@ int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot)
#ifdef CONFIG_ROCKHOPPER
void i8259_init(void)
{
outb(0x11, 0x20); /* Master ICW1 */
outb(I8259_IRQ_BASE, 0x21); /* Master ICW2 */
outb(0x04, 0x21); /* Master ICW3 */
outb(0x01, 0x21); /* Master ICW4 */
outb(0xff, 0x21); /* Master IMW */
outb(0x11, 0xa0); /* Slave ICW1 */
outb(I8259_IRQ_BASE + 8, 0xa1); /* Slave ICW2 */
outb(0x02, 0xa1); /* Slave ICW3 */
outb(0x01, 0xa1); /* Slave ICW4 */
outb(0xff, 0xa1); /* Slave IMW */
init_i8259_irqs();
outb(0x00, 0x4d0);
outb(0x02, 0x4d1); /* USB IRQ9 is level */
......
arch/mips/philips/pnx8550/common/int.c
View file @ e503606c
......@@ -159,7 +159,7 @@ int pnx8550_set_gic_priority(int irq, int priority)
}
static struct irq_chip level_irq_type = {
.typename = "PNX Level IRQ",
.name = "PNX Level IRQ",
.ack = mask_irq,
.mask = mask_irq,
.mask_ack = mask_irq,
......
arch/mips/philips/pnx8550/common/prom.c
View file @ e503606c
......@@ -106,9 +106,8 @@ int get_ethernet_addr(char *ethernet_addr)
return 0;
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
extern int pnx8550_console_port;
......
arch/mips/pmc-sierra/yosemite/dbg_io.c
View file @ e503606c
......@@ -93,7 +93,7 @@
* Functions to READ and WRITE to serial port 1
*/
#define SERIAL_READ_1(ofs) (*((volatile unsigned char*) \
(TITAN_SERIAL_BASE_1 + ofs)
(TITAN_SERIAL_BASE_1 + ofs)))
#define SERIAL_WRITE_1(ofs, val) ((*((volatile unsigned char*) \
(TITAN_SERIAL_BASE_1 + ofs))) = val)
......
arch/mips/pmc-sierra/yosemite/irq.c
View file @ e503606c
......@@ -148,9 +148,9 @@ void __init arch_init_irq(void)
{
clear_c0_status(ST0_IM);
mips_cpu_irq_init(0);
rm7k_cpu_irq_init(8);
rm9k_cpu_irq_init(12);
mips_cpu_irq_init();
rm7k_cpu_irq_init();
rm9k_cpu_irq_init();
#ifdef CONFIG_KGDB
/* At this point, initialize the second serial port */
......
arch/mips/pmc-sierra/yosemite/prom.c
View file @ e503606c
......@@ -132,9 +132,8 @@ void __init prom_init(void)
prom_grab_secondary();
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
......
arch/mips/pmc-sierra/yosemite/setup.c
View file @ e503606c
......@@ -171,6 +171,7 @@ static void __init py_map_ocd(void)
static void __init py_uart_setup(void)
{
#ifdef CONFIG_SERIAL_8250
struct uart_port up;
/*
......@@ -188,6 +189,7 @@ static void __init py_uart_setup(void)
if (early_serial_setup(&up))
printk(KERN_ERR "Early serial init of port 0 failed\n");
#endif /* CONFIG_SERIAL_8250 */
}
static void __init py_rtc_setup(void)
......
arch/mips/qemu/q-mem.c
View file @ e503606c
#include <linux/init.h>
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0UL;
}
arch/mips/sgi-ip22/ip22-eisa.c
View file @ e503606c
......@@ -139,7 +139,7 @@ static void end_eisa1_irq(unsigned int irq)
}
static struct irq_chip ip22_eisa1_irq_type = {
.typename = "IP22 EISA",
.name = "IP22 EISA",
.startup = startup_eisa1_irq,
.ack = mask_and_ack_eisa1_irq,
.mask = disable_eisa1_irq,
......@@ -194,7 +194,7 @@ static void end_eisa2_irq(unsigned int irq)
}
static struct irq_chip ip22_eisa2_irq_type = {
.typename = "IP22 EISA",
.name = "IP22 EISA",
.startup = startup_eisa2_irq,
.ack = mask_and_ack_eisa2_irq,
.mask = disable_eisa2_irq,
......
arch/mips/sgi-ip22/ip22-int.c
View file @ e503606c
......@@ -19,6 +19,7 @@
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/irq_cpu.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/hpc3.h>
......@@ -52,7 +53,7 @@ static void disable_local0_irq(unsigned int irq)
}
static struct irq_chip ip22_local0_irq_type = {
.typename = "IP22 local 0",
.name = "IP22 local 0",
.ack = disable_local0_irq,
.mask = disable_local0_irq,
.mask_ack = disable_local0_irq,
......@@ -73,7 +74,7 @@ void disable_local1_irq(unsigned int irq)
}
static struct irq_chip ip22_local1_irq_type = {
.typename = "IP22 local 1",
.name = "IP22 local 1",
.ack = disable_local1_irq,
.mask = disable_local1_irq,
.mask_ack = disable_local1_irq,
......@@ -94,7 +95,7 @@ void disable_local2_irq(unsigned int irq)
}
static struct irq_chip ip22_local2_irq_type = {
.typename = "IP22 local 2",
.name = "IP22 local 2",
.ack = disable_local2_irq,
.mask = disable_local2_irq,
.mask_ack = disable_local2_irq,
......@@ -115,7 +116,7 @@ void disable_local3_irq(unsigned int irq)
}
static struct irq_chip ip22_local3_irq_type = {
.typename = "IP22 local 3",
.name = "IP22 local 3",
.ack = disable_local3_irq,
.mask = disable_local3_irq,
.mask_ack = disable_local3_irq,
......@@ -253,8 +254,6 @@ asmlinkage void plat_irq_dispatch(void)
indy_8254timer_irq();
}
extern void mips_cpu_irq_init(unsigned int irq_base);
void __init arch_init_irq(void)
{
int i;
......@@ -316,7 +315,7 @@ void __init arch_init_irq(void)
sgint->cmeimask1 = 0;
/* init CPU irqs */
mips_cpu_irq_init(SGINT_CPU);
mips_cpu_irq_init();
for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
struct irq_chip *handler;
......
arch/mips/sgi-ip22/ip22-mc.c
View file @ e503606c
......@@ -202,7 +202,6 @@ void __init sgimc_init(void)
}
void __init prom_meminit(void) {}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
arch/mips/sgi-ip27/ip27-irq.c
View file @ e503606c
......@@ -333,7 +333,7 @@ static inline void disable_bridge_irq(unsigned int irq)
}
static struct irq_chip bridge_irq_type = {
.typename = "bridge",
.name = "bridge",
.startup = startup_bridge_irq,
.shutdown = shutdown_bridge_irq,
.ack = disable_bridge_irq,
......
arch/mips/sgi-ip27/ip27-memory.c
View file @ e503606c
......@@ -498,10 +498,9 @@ void __init prom_meminit(void)
}
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
/* We got nothing to free here ... */
return 0;
}
extern void pagetable_init(void);
......
arch/mips/sgi-ip27/ip27-timer.c
View file @ e503606c
......@@ -181,7 +181,7 @@ static void disable_rt_irq(unsigned int irq)
}
static struct irq_chip rt_irq_type = {
.typename = "SN HUB RT timer",
.name = "SN HUB RT timer",
.ack = disable_rt_irq,
.mask = disable_rt_irq,
.mask_ack = disable_rt_irq,
......
arch/mips/sgi-ip32/ip32-irq.c
View file @ e503606c
......@@ -144,7 +144,7 @@ static void end_cpu_irq(unsigned int irq)
}
static struct irq_chip ip32_cpu_interrupt = {
.typename = "IP32 CPU",
.name = "IP32 CPU",
.ack = disable_cpu_irq,
.mask = disable_cpu_irq,
.mask_ack = disable_cpu_irq,
......@@ -193,7 +193,7 @@ static void end_crime_irq(unsigned int irq)
}
static struct irq_chip ip32_crime_interrupt = {
.typename = "IP32 CRIME",
.name = "IP32 CRIME",
.ack = mask_and_ack_crime_irq,
.mask = disable_crime_irq,
.mask_ack = mask_and_ack_crime_irq,
......@@ -234,7 +234,7 @@ static void end_macepci_irq(unsigned int irq)
}
static struct irq_chip ip32_macepci_interrupt = {
.typename = "IP32 MACE PCI",
.name = "IP32 MACE PCI",
.ack = disable_macepci_irq,
.mask = disable_macepci_irq,
.mask_ack = disable_macepci_irq,
......@@ -347,7 +347,7 @@ static void end_maceisa_irq(unsigned irq)
}
static struct irq_chip ip32_maceisa_interrupt = {
.typename = "IP32 MACE ISA",
.name = "IP32 MACE ISA",
.ack = mask_and_ack_maceisa_irq,
.mask = disable_maceisa_irq,
.mask_ack = mask_and_ack_maceisa_irq,
......@@ -379,7 +379,7 @@ static void end_mace_irq(unsigned int irq)
}
static struct irq_chip ip32_mace_interrupt = {
.typename = "IP32 MACE",
.name = "IP32 MACE",
.ack = disable_mace_irq,
.mask = disable_mace_irq,
.mask_ack = disable_mace_irq,
......
arch/mips/sgi-ip32/ip32-memory.c
View file @ e503606c
......@@ -43,7 +43,6 @@ void __init prom_meminit (void)
}
unsigned long __init prom_free_prom_memory (void)
void __init prom_free_prom_memory(void)
{
return 0;
}
arch/mips/sibyte/bcm1480/irq.c
View file @ e503606c
......@@ -82,7 +82,7 @@ extern char sb1250_duart_present[];
#endif
static struct irq_chip bcm1480_irq_type = {
.typename = "BCM1480-IMR",
.name = "BCM1480-IMR",
.ack = ack_bcm1480_irq,
.mask = disable_bcm1480_irq,
.mask_ack = ack_bcm1480_irq,
......
arch/mips/sibyte/cfe/setup.c
View file @ e503606c
......@@ -343,10 +343,9 @@ void __init prom_init(void)
prom_meminit();
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
/* Not sure what I'm supposed to do here. Nothing, I think */
return 0;
}
void prom_putchar(char c)
......
arch/mips/sibyte/sb1250/irq.c
View file @ e503606c
......@@ -67,7 +67,7 @@ extern char sb1250_duart_present[];
#endif
static struct irq_chip sb1250_irq_type = {
.typename = "SB1250-IMR",
.name = "SB1250-IMR",
.ack = ack_sb1250_irq,
.mask = disable_sb1250_irq,
.mask_ack = ack_sb1250_irq,
......
arch/mips/sibyte/sb1250/prom.c
View file @ e503606c
......@@ -87,10 +87,9 @@ void __init prom_init(void)
prom_meminit();
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
/* Not sure what I'm supposed to do here. Nothing, I think */
return 0;
}
void prom_putchar(char c)
......
arch/mips/sni/irq.c
View file @ e503606c
......@@ -37,7 +37,7 @@ static void end_pciasic_irq(unsigned int irq)
}
static struct irq_chip pciasic_irq_type = {
.typename = "ASIC-PCI",
.name = "ASIC-PCI",
.ack = disable_pciasic_irq,
.mask = disable_pciasic_irq,
.mask_ack = disable_pciasic_irq,
......
arch/mips/sni/sniprom.c
View file @ e503606c
......@@ -67,9 +67,8 @@ void prom_printf(char *fmt, ...)
va_end(args);
}
unsigned long prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
/*
......
arch/mips/tx4927/common/tx4927_irq.c
View file @ e503606c
......@@ -120,7 +120,7 @@ static void tx4927_irq_pic_disable(unsigned int irq);
#define TX4927_CP0_NAME "TX4927-CP0"
static struct irq_chip tx4927_irq_cp0_type = {
.typename = TX4927_CP0_NAME,
.name = TX4927_CP0_NAME,
.ack = tx4927_irq_cp0_disable,
.mask = tx4927_irq_cp0_disable,
.mask_ack = tx4927_irq_cp0_disable,
......@@ -129,7 +129,7 @@ static struct irq_chip tx4927_irq_cp0_type = {
#define TX4927_PIC_NAME "TX4927-PIC"
static struct irq_chip tx4927_irq_pic_type = {
.typename = TX4927_PIC_NAME,
.name = TX4927_PIC_NAME,
.ack = tx4927_irq_pic_disable,
.mask = tx4927_irq_pic_disable,
.mask_ack = tx4927_irq_pic_disable,
......
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
View file @ e503606c
......@@ -228,7 +228,7 @@ static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
.typename = TOSHIBA_RBTX4927_IOC_NAME,
.name = TOSHIBA_RBTX4927_IOC_NAME,
.ack = toshiba_rbtx4927_irq_ioc_disable,
.mask = toshiba_rbtx4927_irq_ioc_disable,
.mask_ack = toshiba_rbtx4927_irq_ioc_disable,
......@@ -241,7 +241,7 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
#ifdef CONFIG_TOSHIBA_FPCIB0
#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
.typename = TOSHIBA_RBTX4927_ISA_NAME,
.name = TOSHIBA_RBTX4927_ISA_NAME,
.ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
.mask = toshiba_rbtx4927_irq_isa_disable,
.mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
......@@ -490,13 +490,13 @@ void toshiba_rbtx4927_irq_dump(char *key)
{
u32 i, j = 0;
for (i = 0; i < NR_IRQS; i++) {
if (strcmp(irq_desc[i].chip->typename, "none")
if (strcmp(irq_desc[i].chip->name, "none")
== 0)
continue;
if ((i >= 1)
&& (irq_desc[i - 1].chip->typename ==
irq_desc[i].chip->typename)) {
&& (irq_desc[i - 1].chip->name ==
irq_desc[i].chip->name)) {
j++;
} else {
j = 0;
......@@ -510,7 +510,7 @@ void toshiba_rbtx4927_irq_dump(char *key)
(u32) (irq_desc[i].action ? irq_desc[i].
action->handler : 0),
irq_desc[i].depth,
irq_desc[i].chip->typename, j);
irq_desc[i].chip->name, j);
}
}
#endif
......
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
View file @ e503606c
......@@ -80,9 +80,8 @@ void __init prom_init(void)
add_memory_region(0, msize << 20, BOOT_MEM_RAM);
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
const char *get_system_type(void)
......
arch/mips/tx4938/common/irq.c
View file @ e503606c
......@@ -49,7 +49,7 @@ static void tx4938_irq_pic_disable(unsigned int irq);
#define TX4938_CP0_NAME "TX4938-CP0"
static struct irq_chip tx4938_irq_cp0_type = {
.typename = TX4938_CP0_NAME,
.name = TX4938_CP0_NAME,
.ack = tx4938_irq_cp0_disable,
.mask = tx4938_irq_cp0_disable,
.mask_ack = tx4938_irq_cp0_disable,
......@@ -58,7 +58,7 @@ static struct irq_chip tx4938_irq_cp0_type = {
#define TX4938_PIC_NAME "TX4938-PIC"
static struct irq_chip tx4938_irq_pic_type = {
.typename = TX4938_PIC_NAME,
.name = TX4938_PIC_NAME,
.ack = tx4938_irq_pic_disable,
.mask = tx4938_irq_pic_disable,
.mask_ack = tx4938_irq_pic_disable,
......
arch/mips/tx4938/toshiba_rbtx4938/irq.c
View file @ e503606c
......@@ -92,7 +92,7 @@ static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
.typename = TOSHIBA_RBTX4938_IOC_NAME,
.name = TOSHIBA_RBTX4938_IOC_NAME,
.ack = toshiba_rbtx4938_irq_ioc_disable,
.mask = toshiba_rbtx4938_irq_ioc_disable,
.mask_ack = toshiba_rbtx4938_irq_ioc_disable,
......
arch/mips/tx4938/toshiba_rbtx4938/prom.c
View file @ e503606c
......@@ -56,9 +56,8 @@ void __init prom_init(void)
return;
}
unsigned long __init prom_free_prom_memory(void)
void __init prom_free_prom_memory(void)
{
return 0;
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
......
arch/mips/vr41xx/common/icu.c
View file @ e503606c
......@@ -3,7 +3,7 @@
*
* Copyright (C) 2001-2002 MontaVista Software Inc.
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
* Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -68,6 +68,7 @@ static unsigned char sysint2_assign[16] = {
#define MPIUINTREG 0x0e
#define MAIUINTREG 0x10
#define MKIUINTREG 0x12
#define MMACINTREG 0x12
#define MGIUINTLREG 0x14
#define MDSIUINTREG 0x16
#define NMIREG 0x18
......@@ -241,6 +242,30 @@ void vr41xx_disable_kiuint(uint16_t mask)
EXPORT_SYMBOL(vr41xx_disable_kiuint);
void vr41xx_enable_macint(uint16_t mask)
{
struct irq_desc *desc = irq_desc + ETHERNET_IRQ;
unsigned long flags;
spin_lock_irqsave(&desc->lock, flags);
icu1_set(MMACINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
}
EXPORT_SYMBOL(vr41xx_enable_macint);
void vr41xx_disable_macint(uint16_t mask)
{
struct irq_desc *desc = irq_desc + ETHERNET_IRQ;
unsigned long flags;
spin_lock_irqsave(&desc->lock, flags);
icu1_clear(MMACINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
}
EXPORT_SYMBOL(vr41xx_disable_macint);
void vr41xx_enable_dsiuint(uint16_t mask)
{
struct irq_desc *desc = irq_desc + DSIU_IRQ;
......@@ -428,7 +453,7 @@ static void enable_sysint1_irq(unsigned int irq)
}
static struct irq_chip sysint1_irq_type = {
.typename = "SYSINT1",
.name = "SYSINT1",
.ack = disable_sysint1_irq,
.mask = disable_sysint1_irq,
.mask_ack = disable_sysint1_irq,
......@@ -446,7 +471,7 @@ static void enable_sysint2_irq(unsigned int irq)
}
static struct irq_chip sysint2_irq_type = {
.typename = "SYSINT2",
.name = "SYSINT2",
.ack = disable_sysint2_irq,
.mask = disable_sysint2_irq,
.mask_ack = disable_sysint2_irq,
......
arch/mips/vr41xx/common/init.c
View file @ e503606c
......@@ -81,7 +81,6 @@ void __init prom_init(void)
}
}
unsigned long __init prom_free_prom_memory (void)
void __init prom_free_prom_memory(void)
{
return 0UL;
}
arch/mips/vr41xx/common/irq.c
View file @ e503606c
......@@ -95,27 +95,27 @@ asmlinkage void plat_irq_dispatch(void)
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & CAUSEF_IP7)
do_IRQ(7);
do_IRQ(TIMER_IRQ);
else if (pending & 0x7800) {
if (pending & CAUSEF_IP3)
irq_dispatch(3);
irq_dispatch(INT1_IRQ);
else if (pending & CAUSEF_IP4)
irq_dispatch(4);
irq_dispatch(INT2_IRQ);
else if (pending & CAUSEF_IP5)
irq_dispatch(5);
irq_dispatch(INT3_IRQ);
else if (pending & CAUSEF_IP6)
irq_dispatch(6);
irq_dispatch(INT4_IRQ);
} else if (pending & CAUSEF_IP2)
irq_dispatch(2);
irq_dispatch(INT0_IRQ);
else if (pending & CAUSEF_IP0)
do_IRQ(0);
do_IRQ(MIPS_SOFTINT0_IRQ);
else if (pending & CAUSEF_IP1)
do_IRQ(1);
do_IRQ(MIPS_SOFTINT1_IRQ);
else
spurious_interrupt();
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
mips_cpu_irq_init();
}
arch/mips/vr41xx/nec-cmbvr4133/irq.c
View file @ e503606c
......@@ -21,60 +21,16 @@
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/i8259.h>
#include <asm/vr41xx/cmbvr4133.h>
extern void enable_8259A_irq(unsigned int irq);
extern void disable_8259A_irq(unsigned int irq);
extern void mask_and_ack_8259A(unsigned int irq);
extern void init_8259A(int hoge);
extern int vr4133_rockhopper;
static void enable_i8259_irq(unsigned int irq)
{
enable_8259A_irq(irq - I8259_IRQ_BASE);
}
static void disable_i8259_irq(unsigned int irq)
{
disable_8259A_irq(irq - I8259_IRQ_BASE);
}
static void ack_i8259_irq(unsigned int irq)
{
mask_and_ack_8259A(irq - I8259_IRQ_BASE);
}
static struct irq_chip i8259_irq_type = {
.typename = "XT-PIC",
.ack = ack_i8259_irq,
.mask = disable_i8259_irq,
.mask_ack = ack_i8259_irq,
.unmask = enable_i8259_irq,
};
static int i8259_get_irq_number(int irq)
{
unsigned long isr;
isr = inb(0x20);
irq = ffz(~isr);
if (irq == 2) {
isr = inb(0xa0);
irq = 8 + ffz(~isr);
}
if (irq < 0 || irq > 15)
return -EINVAL;
return I8259_IRQ_BASE + irq;
return i8259_irq();
}
static struct irqaction i8259_slave_cascade = {
.handler = &no_action,
.name = "cascade",
};
void __init rockhopper_init_irq(void)
{
int i;
......@@ -84,11 +40,6 @@ void __init rockhopper_init_irq(void)
return;
}
for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
set_irq_chip_and_handler(i, &i8259_irq_type, handle_level_irq);
setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH);
vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number);
......
include/asm-mips/bootinfo.h
View file @ e503606c
......@@ -243,6 +243,10 @@ extern struct boot_mem_map boot_mem_map;
extern void add_memory_region(phys_t start, phys_t size, long type);
extern void prom_init(void);
extern void prom_free_prom_memory(void);
extern void free_init_pages(const char *what,
unsigned long begin, unsigned long end);
/*
* Initial kernel command line, usually setup by prom_init()
......
include/asm-mips/ddb5xxx/ddb5477.h
View file @ e503606c
......@@ -17,6 +17,7 @@
#ifndef __ASM_DDB5XXX_DDB5477_H
#define __ASM_DDB5XXX_DDB5477_H
#include <irq.h>
/*
* This contains macros that are specific to DDB5477 or renamed from
......@@ -251,14 +252,10 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
*/
#define NUM_CPU_IRQ 8
#define NUM_I8259_IRQ 16
#define NUM_VRC5477_IRQ 32
#define DDB_IRQ_BASE 0
#define I8259_IRQ_BASE DDB_IRQ_BASE
#define VRC5477_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
#define CPU_IRQ_BASE (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ)
#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
/*
* vrc5477 irq defs
......@@ -300,22 +297,22 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
#define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE)
#define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A (4 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_PARALLEL (5 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_RESERVED_6 (6 + I8259_IRQ_BASE)
#define I8259_IRQ_RESERVED_7 (7 + I8259_IRQ_BASE)
#define I8259_IRQ_RTC (8 + I8259_IRQ_BASE) /* who set this? */
#define I8259_IRQ_USB (9 + I8259_IRQ_BASE) /* ddb_setup */
#define I8259_IRQ_PMU (10 + I8259_IRQ_BASE) /* ddb_setup */
#define I8259_IRQ_RESERVED_11 (11 + I8259_IRQ_BASE)
#define I8259_IRQ_RESERVED_12 (12 + I8259_IRQ_BASE) /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 (13 + I8259_IRQ_BASE)
#define I8259_IRQ_HDC1 (14 + I8259_IRQ_BASE) /* default and ddb_setup */
#define I8259_IRQ_HDC2 (15 + I8259_IRQ_BASE) /* default */
#define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE)
#define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE)
#define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE)
#define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE)
#define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */
#define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */
#define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */
#define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE)
#define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE)
#define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */
#define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */
/*
......
include/asm-mips/dec/interrupts.h
View file @ e503606c
......@@ -14,6 +14,7 @@
#ifndef __ASM_DEC_INTERRUPTS_H
#define __ASM_DEC_INTERRUPTS_H
#include <irq.h>
#include <asm/mipsregs.h>
......@@ -87,7 +88,7 @@
#define DEC_CPU_INR_SW1 1 /* software #1 */
#define DEC_CPU_INR_SW0 0 /* software #0 */
#define DEC_CPU_IRQ_BASE 0 /* first IRQ assigned to CPU */
#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE)
#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
......
include/asm-mips/dma.h
View file @ e503606c
......@@ -91,6 +91,7 @@
#else
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#endif
#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
......
include/asm-mips/emma2rh/emma2rh.h
View file @ e503606c
......@@ -24,6 +24,8 @@
#ifndef __ASM_EMMA2RH_EMMA2RH_H
#define __ASM_EMMA2RH_EMMA2RH_H
#include <irq.h>
/*
* EMMA2RH registers
*/
......@@ -104,7 +106,8 @@
#define NUM_EMMA2RH_IRQ 96
#define CPU_EMMA2RH_CASCADE 2
#define EMMA2RH_IRQ_BASE 0
#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
/*
* emma2rh irq defs
......
include/asm-mips/emma2rh/markeins.h
View file @ e503606c
......@@ -33,7 +33,6 @@
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
#define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
......
include/asm-mips/i8259.h
View file @ e503606c
......@@ -18,6 +18,7 @@
#include <linux/spinlock.h>
#include <asm/io.h>
#include <irq.h>
/* i8259A PIC registers */
#define PIC_MASTER_CMD 0x20
......@@ -42,8 +43,6 @@ extern void disable_8259A_irq(unsigned int irq);
extern void init_i8259_irqs(void);
#define I8259A_IRQ_BASE 0
/*
* Do the traditional i8259 interrupt polling thing. This is for the few
* cases where no better interrupt acknowledge method is available and we
......
include/asm-mips/io.h
View file @ e503606c
......@@ -115,7 +115,7 @@ static inline void set_io_port_base(unsigned long base)
*/
static inline unsigned long virt_to_phys(volatile const void *address)
{
return (unsigned long)address - PAGE_OFFSET;
return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET;
}
/*
......@@ -132,7 +132,7 @@ static inline unsigned long virt_to_phys(volatile const void *address)
*/
static inline void * phys_to_virt(unsigned long address)
{
return (void *)(address + PAGE_OFFSET);
return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
}
/*
......
include/asm-mips/irq.h
View file @ e503606c
......@@ -18,7 +18,7 @@
#ifdef CONFIG_I8259
static inline int irq_canonicalize(int irq)
{
return ((irq == 2) ? 9 : irq);
return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
}
#else
#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
......
include/asm-mips/irq_cpu.h
View file @ e503606c
......@@ -13,8 +13,8 @@
#ifndef _ASM_IRQ_CPU_H
#define _ASM_IRQ_CPU_H
extern void mips_cpu_irq_init(int irq_base);
extern void rm7k_cpu_irq_init(int irq_base);
extern void rm9k_cpu_irq_init(int irq_base);
extern void mips_cpu_irq_init(void);
extern void rm7k_cpu_irq_init(void);
extern void rm9k_cpu_irq_init(void);
#endif /* _ASM_IRQ_CPU_H */
include/asm-mips/mach-au1x00/au1000.h
View file @ e503606c
......@@ -39,6 +39,7 @@
#ifndef _LANGUAGE_ASSEMBLY
#include <linux/delay.h>
#include <linux/types.h>
#include <asm/io.h>
/* cpu pipeline flush */
......
include/asm-mips/mach-cobalt/cobalt.h
View file @ e503606c
......@@ -12,6 +12,8 @@
#ifndef __ASM_COBALT_H
#define __ASM_COBALT_H
#include <irq.h>
/*
* i8259 legacy interrupts used on Cobalt:
*
......@@ -25,7 +27,7 @@
/*
* CPU IRQs are 16 ... 23
*/
#define COBALT_CPU_IRQ 16
#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
......
include/asm-mips/mach-emma2rh/irq.h
View file @ e503606c
......@@ -10,4 +10,6 @@
#define NR_IRQS 256
#include_next <irq.h>
#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
include/asm-mips/mach-generic/irq.h
View file @ e503606c
......@@ -8,6 +8,38 @@
#ifndef __ASM_MACH_GENERIC_IRQ_H
#define __ASM_MACH_GENERIC_IRQ_H
#ifndef NR_IRQS
#define NR_IRQS 128
#endif
#ifdef CONFIG_I8259
#ifndef I8259A_IRQ_BASE
#define I8259A_IRQ_BASE 0
#endif
#endif
#ifdef CONFIG_IRQ_CPU
#ifndef MIPS_CPU_IRQ_BASE
#ifdef CONFIG_I8259
#define MIPS_CPU_IRQ_BASE 16
#else
#define MIPS_CPU_IRQ_BASE 0
#endif /* CONFIG_I8259 */
#endif
#ifdef CONFIG_IRQ_CPU_RM7K
#ifndef RM7K_CPU_IRQ_BASE
#define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
#endif
#endif
#ifdef CONFIG_IRQ_CPU_RM9K
#ifndef RM9K_CPU_IRQ_BASE
#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
#endif
#endif
#endif /* CONFIG_IRQ_CPU */
#endif /* __ASM_MACH_GENERIC_IRQ_H */
include/asm-mips/mach-mips/irq.h
View file @ e503606c
......@@ -4,4 +4,6 @@
#define NR_IRQS 256
#include_next <irq.h>
#endif /* __ASM_MACH_MIPS_IRQ_H */
include/asm-mips/mach-vr41xx/irq.h 0 → 100644
View file @ e503606c
#ifndef __ASM_MACH_VR41XX_IRQ_H
#define __ASM_MACH_VR41XX_IRQ_H
#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
#ifdef CONFIG_NEC_CMBVR4133
#include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */
#endif
#include_next <irq.h>
#endif /* __ASM_MACH_VR41XX_IRQ_H */
include/asm-mips/mips-boards/atlasint.h
View file @ e503606c
......@@ -26,10 +26,12 @@
#ifndef _MIPS_ATLASINT_H
#define _MIPS_ATLASINT_H
#include <irq.h>
/*
* Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
*/
#define MIPSCPU_INT_BASE 0
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
/* CPU interrupt offsets */
#define MIPSCPU_INT_SW0 0
......
include/asm-mips/mips-boards/maltaint.h
View file @ e503606c
......@@ -25,6 +25,8 @@
#ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H
#include <irq.h>
/*
* Interrupts 0..15 are used for Malta ISA compatible interrupts
*/
......@@ -33,7 +35,7 @@
/*
* Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
*/
#define MIPSCPU_INT_BASE 16
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
/* CPU interrupt offsets */
#define MIPSCPU_INT_SW0 0
......
include/asm-mips/mips-boards/prom.h
View file @ e503606c
......@@ -33,7 +33,6 @@ extern void prom_printf(char *fmt, ...);
extern void prom_init_cmdline(void);
extern void prom_meminit(void);
extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
extern unsigned long prom_free_prom_memory (void);
extern void mips_display_message(const char *str);
extern void mips_display_word(unsigned int num);
extern int get_ethernet_addr(char *ethernet_addr);
......
include/asm-mips/mips-boards/seadint.h
View file @ e503606c
......@@ -20,10 +20,12 @@
#ifndef _MIPS_SEADINT_H
#define _MIPS_SEADINT_H
#include <irq.h>
/*
* Interrupts 0..7 are used for SEAD CPU interrupts
*/
#define MIPSCPU_INT_BASE 0
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
#define MIPSCPU_INT_UART0 2
#define MIPSCPU_INT_UART1 3
......
include/asm-mips/mips-boards/simint.h
View file @ e503606c
......@@ -17,10 +17,11 @@
#ifndef _MIPS_SIMINT_H
#define _MIPS_SIMINT_H
#include <irq.h>
#define SIM_INT_BASE 0
#define MIPSCPU_INT_MB0 2
#define MIPSCPU_INT_BASE 16
#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
#define MIPS_CPU_TIMER_IRQ 7
......
include/asm-mips/mipsmtregs.h
View file @ e503606c
......@@ -165,8 +165,6 @@
#ifndef __ASSEMBLY__
extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
static inline unsigned int dvpe(void)
{
int res = 0;
......
include/asm-mips/page.h
View file @ e503606c
......@@ -34,6 +34,20 @@
#ifndef __ASSEMBLY__
/*
* This gives the physical RAM offset.
*/
#ifndef PHYS_OFFSET
#define PHYS_OFFSET 0UL
#endif
/*
* It's normally defined only for FLATMEM config but it's
* used in our early mem init code for all memory models.
* So always define it.
*/
#define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET)
#include <linux/pfn.h>
#include <asm/io.h>
......@@ -132,20 +146,23 @@ typedef struct { unsigned long pgprot; } pgprot_t;
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
/*
* __pa()/__va() should be used only during mem init.
*/
#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
#define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0)
#else
#define __pa_page_offset(x) PAGE_OFFSET
#endif
#define __pa(x) ((unsigned long)(x) - __pa_page_offset(x))
#define __pa(x) ((unsigned long)(x) - __pa_page_offset(x) + PHYS_OFFSET)
#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0))
#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) ((pfn) < max_mapnr)
#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr)
#elif defined(CONFIG_SPARSEMEM)
......
include/asm-mips/rtlx.h
View file @ e503606c
......@@ -6,9 +6,10 @@
#ifndef __ASM_RTLX_H
#define __ASM_RTLX_H_
#include <irq.h>
#define LX_NODE_BASE 10
#define MIPSCPU_INT_BASE 16
#define MIPS_CPU_RTLX_IRQ 0
#define RTLX_VERSION 2
......
include/asm-mips/sections.h
View file @ e503606c
......@@ -3,6 +3,4 @@
#include <asm-generic/sections.h>
extern char _fdata;
#endif /* _ASM_SECTIONS_H */
include/asm-mips/sgi/ip22.h
View file @ e503606c
......@@ -21,15 +21,16 @@
* HAL2 driver). This will prevent many complications, trust me ;-)
*/
#include <irq.h>
#include <asm/sgi/ioc.h>
#define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */
#define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */
#define SGINT_LOCAL0 24 /* 8 local0 irq levels */
#define SGINT_LOCAL1 32 /* 8 local1 irq levels */
#define SGINT_LOCAL2 40 /* 8 local2 vectored irq levels */
#define SGINT_LOCAL3 48 /* 8 local3 vectored irq levels */
#define SGINT_END 56 /* End of 'spaces' */
#define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
#define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */
#define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */
#define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */
#define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */
#define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */
/*
* Individual interrupt definitions for the Indy and Indigo2
......
include/asm-mips/smtc_ipi.h
View file @ e503606c
......@@ -44,9 +44,6 @@ struct smtc_ipi_q {
int depth;
};
extern struct smtc_ipi_q IPIQ[NR_CPUS];
extern struct smtc_ipi_q freeIPIq;
static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
{
long flags;
......
include/asm-mips/uaccess.h
View file @ e503606c
......@@ -488,7 +488,8 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
})
/*
* __copy_from_user: - Copy a block of data from user space, with less checking. * @to: Destination address, in kernel space.
* __copy_from_user: - Copy a block of data from user space, with less checking.
* @to: Destination address, in kernel space.
* @from: Source address, in user space.
* @n: Number of bytes to copy.
*
......
include/asm-mips/vr41xx/cmbvr4133.h
View file @ e503606c
......@@ -35,8 +35,8 @@
#define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN)
#define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN)
#define I8259_IRQ_BASE 72
#define I8259_IRQ(x) (I8259_IRQ_BASE + (x))
#define I8259A_IRQ_BASE 72
#define I8259_IRQ(x) (I8259A_IRQ_BASE + (x))
#define TIMER_IRQ I8259_IRQ(0)
#define KEYBOARD_IRQ I8259_IRQ(1)
#define I8259_SLAVE_IRQ I8259_IRQ(2)
......@@ -52,6 +52,5 @@
#define AUX_IRQ I8259_IRQ(12)
#define IDE_PRIMARY_IRQ I8259_IRQ(14)
#define IDE_SECONDARY_IRQ I8259_IRQ(15)
#define I8259_IRQ_LAST IDE_SECONDARY_IRQ
#endif /* __NEC_CMBVR4133_H */
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