Commit e51e07e0 authored by Tkhai Kirill's avatar Tkhai Kirill Committed by David S. Miller

sparc32: forced setting of mode of sun4m per-cpu timers

SUN4M per-cpu timers have two modes of work. These are timer mode and
counter mode. Kernel doesn't write anything to the register, which is
connected with mode choice.
So, the mode is chosen by bootloader. This patch forces to use timer
mode from the kernel and to be independent of bootloader.

I had this problem with OpenBIOS. Timers don't tick and kernel fails on
QEMU, when it's compiled with SMP support. The patch fixes problem.
Signed-off-by: default avatarTkhai Kirill <tkhai@yandex.ru>
Acked-by: default avatarSam Ravnborg <sam@ravnborg.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7b3480f8
...@@ -399,6 +399,9 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn) ...@@ -399,6 +399,9 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
timers_global = (void __iomem *) timers_global = (void __iomem *)
(unsigned long) addr[num_cpu_timers]; (unsigned long) addr[num_cpu_timers];
/* Every per-cpu timer works in timer mode */
sbus_writel(0x00000000, &timers_global->timer_config);
sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit); sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
master_l10_counter = &timers_global->l10_count; master_l10_counter = &timers_global->l10_count;
......
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