Commit e53f21c7 authored by Zdenko Pulitika's avatar Zdenko Pulitika Committed by Stephen Boyd

clk: pistachio: Fix override of clk-pll settings from boot loader

PLL enable callbacks are overriding PLL mode (int/frac) and
Noise reduction (on/off) settings set by the boot loader which
results in the incorrect clock rate.

PLL mode and noise reduction are defined by the DSMPD and DACPD bits
of the PLL control register. PLL .enable() callbacks enable PLL
by deasserting all power-down bits of the PLL control register,
including DSMPD and DACPD bits, which is not necessary since
these bits don't actually enable/disable PLL.

This commit fixes the problem by removing DSMPD and DACPD bits
from the "PLL enable" mask.

Fixes: 43049b0c("CLK: Pistachio: Add PLL driver")
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: default avatarAndrew Bresitcker <abrestic@chromium.org>
Signed-off-by: default avatarZdenko Pulitika <zdenko.pulitika@imgtec.com>
Signed-off-by: default avatarGovindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 093affb0
...@@ -134,8 +134,7 @@ static int pll_gf40lp_frac_enable(struct clk_hw *hw) ...@@ -134,8 +134,7 @@ static int pll_gf40lp_frac_enable(struct clk_hw *hw)
u32 val; u32 val;
val = pll_readl(pll, PLL_CTRL3); val = pll_readl(pll, PLL_CTRL3);
val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_DACPD | val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD |
PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD |
PLL_FRAC_CTRL3_FOUT4PHASEPD | PLL_FRAC_CTRL3_FOUTVCOPD); PLL_FRAC_CTRL3_FOUT4PHASEPD | PLL_FRAC_CTRL3_FOUTVCOPD);
pll_writel(pll, val, PLL_CTRL3); pll_writel(pll, val, PLL_CTRL3);
...@@ -277,7 +276,7 @@ static int pll_gf40lp_laint_enable(struct clk_hw *hw) ...@@ -277,7 +276,7 @@ static int pll_gf40lp_laint_enable(struct clk_hw *hw)
u32 val; u32 val;
val = pll_readl(pll, PLL_CTRL1); val = pll_readl(pll, PLL_CTRL1);
val &= ~(PLL_INT_CTRL1_PD | PLL_INT_CTRL1_DSMPD | val &= ~(PLL_INT_CTRL1_PD |
PLL_INT_CTRL1_FOUTPOSTDIVPD | PLL_INT_CTRL1_FOUTVCOPD); PLL_INT_CTRL1_FOUTPOSTDIVPD | PLL_INT_CTRL1_FOUTVCOPD);
pll_writel(pll, val, PLL_CTRL1); pll_writel(pll, val, PLL_CTRL1);
......
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