Commit e5d2bd41 authored by Trevor Wu's avatar Trevor Wu Committed by Mark Brown

ASoC: mediatek: mt8188: revise ETDM control flow

Replace register controls in snd_soc_dai_ops with snd_soc_dapm_widgets.
startup, shutdown and trigger ops are removed, and create DAPM_SUPPLY
to handle mclk, clock gating and etdm enabling. Additionally, mclk setup
sequence is also updated because of new supply enabling sequence.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com
Link: https://lore.kernel.org/r/20230510035526.18137-4-trevor.wu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org
parent 2664c879
This diff is collapsed.
...@@ -3007,6 +3007,7 @@ ...@@ -3007,6 +3007,7 @@
#define ETDM_CON0_SLAVE_MODE BIT(5) #define ETDM_CON0_SLAVE_MODE BIT(5)
#define ETDM_CON0_SYNC_MODE BIT(1) #define ETDM_CON0_SYNC_MODE BIT(1)
#define ETDM_CON0_EN BIT(0) #define ETDM_CON0_EN BIT(0)
#define ETDM_CON0_EN_SHIFT 0
#define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28) #define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28)
...@@ -3108,6 +3109,7 @@ ...@@ -3108,6 +3109,7 @@
#define AFE_DPTX_CON_CH_NUM_8CH (0x1 << 1) #define AFE_DPTX_CON_CH_NUM_8CH (0x1 << 1)
#define AFE_DPTX_CON_CH_NUM_MASK BIT(1) #define AFE_DPTX_CON_CH_NUM_MASK BIT(1)
#define AFE_DPTX_CON_ON BIT(0) #define AFE_DPTX_CON_ON BIT(0)
#define AFE_DPTX_CON_ON_SHIFT 0
/* AFE_ADDA_DL_SRC2_CON0 */ /* AFE_ADDA_DL_SRC2_CON0 */
#define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28) #define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment