Commit e63b063e authored by Jerome Brunet's avatar Jerome Brunet

clk: meson: fix MPLL 50M binding id typo

MPLL_5OM (the capital letter o) should indeed be MPLL_50M (the number)
Fix this before it gets used.

Fixes: 25db146a ("dt-bindings: clk: meson: add g12a periph clock controller bindings")
Reported-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent a188339c
...@@ -2734,8 +2734,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { ...@@ -2734,8 +2734,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
[CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
[CLKID_MALI_1] = &g12a_mali_1.hw, [CLKID_MALI_1] = &g12a_mali_1.hw,
[CLKID_MALI] = &g12a_mali.hw, [CLKID_MALI] = &g12a_mali.hw,
[CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw, [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
[CLKID_MPLL_5OM] = &g12a_mpll_50m.hw, [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
......
...@@ -166,7 +166,7 @@ ...@@ -166,7 +166,7 @@
#define CLKID_HDMI_DIV 167 #define CLKID_HDMI_DIV 167
#define CLKID_MALI_0_DIV 170 #define CLKID_MALI_0_DIV 170
#define CLKID_MALI_1_DIV 173 #define CLKID_MALI_1_DIV 173
#define CLKID_MPLL_5OM_DIV 176 #define CLKID_MPLL_50M_DIV 176
#define CLKID_SYS_PLL_DIV16_EN 178 #define CLKID_SYS_PLL_DIV16_EN 178
#define CLKID_SYS_PLL_DIV16 179 #define CLKID_SYS_PLL_DIV16 179
#define CLKID_CPU_CLK_DYN0_SEL 180 #define CLKID_CPU_CLK_DYN0_SEL 180
......
...@@ -130,7 +130,7 @@ ...@@ -130,7 +130,7 @@
#define CLKID_MALI_1_SEL 172 #define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174 #define CLKID_MALI_1 174
#define CLKID_MALI 175 #define CLKID_MALI 175
#define CLKID_MPLL_5OM 177 #define CLKID_MPLL_50M 177
#define CLKID_CPU_CLK 187 #define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201 #define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204 #define CLKID_VDEC_1 204
......
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