drm/amd/powerplay: maximum code sharing around watermarks setting

Maximum code sharing.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

@@ -1486,22 +1486,11 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
 		return 0;
 	}
 
-	mutex_lock(&smu->mutex);
-
-	/* pass data to smu controller */
-	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
-			!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 	ret = smu_write_watermarks_table(smu);
-
 	if (ret) {
-			mutex_unlock(&smu->mutex);
 		DRM_ERROR("Failed to update WMTABLE!\n");
 		return ret;
 	}
-		smu->watermarks_bitmap |= WATERMARKS_LOADED;
-	}
-
-	mutex_unlock(&smu->mutex);
 
 	return 0;
 }

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

@@ -1706,35 +1706,34 @@ int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
 
 int smu_write_watermarks_table(struct smu_context *smu)
 {
-	void *watermarks_table = smu->smu_table.watermarks_table;
+	int ret = 0;
 
-	if (!watermarks_table)
-		return -EINVAL;
+	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
+		return -EOPNOTSUPP;
 
-	return smu_update_table(smu,
-				SMU_TABLE_WATERMARKS,
-				0,
-				watermarks_table,
-				true);
+	mutex_lock(&smu->mutex);
+
+	ret = smu_set_watermarks_table(smu, NULL);
+
+	mutex_unlock(&smu->mutex);
+
+	return ret;
 }
 
 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
 		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
 {
-	void *table = smu->smu_table.watermarks_table;
+	int ret = 0;
 
 	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 		return -EOPNOTSUPP;
 
-	if (!table)
-		return -EINVAL;
-
 	mutex_lock(&smu->mutex);
 
 	if (!smu->disable_watermark &&
 			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
-		smu_set_watermarks_table(smu, table, clock_ranges);
+		ret = smu_set_watermarks_table(smu, clock_ranges);
 
 		if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
 			smu->watermarks_bitmap |= WATERMARKS_EXIST;
@@ -1744,7 +1743,7 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
 
 	mutex_unlock(&smu->mutex);
 
-	return 0;
+	return ret;
 }
 
 int smu_set_ac_dc(struct smu_context *smu)

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

@@ -493,7 +493,7 @@ struct pptable_funcs {
 	int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
 	int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
 	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
-	int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
+	int (*set_watermarks_table)(struct smu_context *smu,
 				    struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
 	int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
 	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

@@ -1577,17 +1577,13 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
 }
 
 static int navi10_set_watermarks_table(struct smu_context *smu,
-				       void *watermarks, struct
-				       dm_pp_wm_sets_with_clock_ranges_soc15
-				       *clock_ranges)
+				       struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
 {
-	int i;
+	Watermarks_t *table = smu->smu_table.watermarks_table;
 	int ret = 0;
-	Watermarks_t *table = watermarks;
-
-	if (!table || !clock_ranges)
-		return -EINVAL;
+	int i;
 
+	if (clock_ranges) {
 		if (clock_ranges->num_wm_dmif_sets > 4 ||
 		    clock_ranges->num_wm_mcif_sets > 4)
 			return -EINVAL;
@@ -1635,9 +1631,11 @@ static int navi10_set_watermarks_table(struct smu_context *smu,
 		}
 
 		smu->watermarks_bitmap |= WATERMARKS_EXIST;
+	}
 
 	/* pass data to smu controller */
-	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 		ret = smu_write_watermarks_table(smu);
 		if (ret) {
 			dev_err(smu->adev->dev, "Failed to update WMTABLE!");

drivers/gpu/drm/amd/powerplay/renoir_ppt.c

@@ -841,16 +841,13 @@ static int renoir_set_performance_level(struct smu_context *smu,
  */
 static int renoir_set_watermarks_table(
 		struct smu_context *smu,
-		void *watermarks,
 		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
 {
-	int i;
+	Watermarks_t *table = smu->smu_table.watermarks_table;
 	int ret = 0;
-	Watermarks_t *table = watermarks;
-
-	if (!table || !clock_ranges)
-		return -EINVAL;
+	int i;
 
+	if (clock_ranges) {
 		if (clock_ranges->num_wm_dmif_sets > 4 ||
 				clock_ranges->num_wm_mcif_sets > 4)
 			return -EINVAL;
@@ -891,9 +888,11 @@ static int renoir_set_watermarks_table(
 		}
 
 		smu->watermarks_bitmap |= WATERMARKS_EXIST;
+	}
 
 	/* pass data to smu controller */
-	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 		ret = smu_write_watermarks_table(smu);
 		if (ret) {
 			dev_err(smu->adev->dev, "Failed to update WMTABLE!");

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

@@ -1380,17 +1380,14 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
 }
 
 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
-				       void *watermarks, struct
-				       dm_pp_wm_sets_with_clock_ranges_soc15
+					       struct dm_pp_wm_sets_with_clock_ranges_soc15
 					       *clock_ranges)
 {
-	int i;
+	Watermarks_t *table = smu->smu_table.watermarks_table;
 	int ret = 0;
-	Watermarks_t *table = watermarks;
-
-	if (!table || !clock_ranges)
-		return -EINVAL;
+	int i;
 
+	if (clock_ranges) {
 		if (clock_ranges->num_wm_dmif_sets > 4 ||
 		    clock_ranges->num_wm_mcif_sets > 4)
 			return -EINVAL;
@@ -1438,8 +1435,10 @@ static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
 		}
 
 		smu->watermarks_bitmap |= WATERMARKS_EXIST;
+	}
 
-	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 		ret = smu_write_watermarks_table(smu);
 		if (ret) {
 			dev_err(smu->adev->dev, "Failed to update WMTABLE!");

drivers/gpu/drm/amd/powerplay/smu_internal.h

@@ -79,7 +79,7 @@
 #define smu_get_current_shallow_sleep_clocks(smu, clocks)		smu_ppt_funcs(get_current_shallow_sleep_clocks, 0, smu, clocks)
 #define smu_dpm_set_vcn_enable(smu, enable)				smu_ppt_funcs(dpm_set_vcn_enable, 0, smu, enable)
 #define smu_dpm_set_jpeg_enable(smu, enable)				smu_ppt_funcs(dpm_set_jpeg_enable, 0, smu, enable)
-#define smu_set_watermarks_table(smu, tab, clock_ranges)		smu_ppt_funcs(set_watermarks_table, 0, smu, tab, clock_ranges)
+#define smu_set_watermarks_table(smu, clock_ranges)			smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges)
 #define smu_thermal_temperature_range_update(smu, range, rw)		smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw)
 #define smu_register_irq_handler(smu)					smu_ppt_funcs(register_irq_handler, 0, smu)
 #define smu_get_dpm_ultimate_freq(smu, param, min, max)			smu_ppt_funcs(get_dpm_ultimate_freq, 0, smu, param, min, max)