Commit e8486ca9 authored by Maxime Chevallier's avatar Maxime Chevallier Committed by David S. Miller

net: mvpp2: cls: Bypass C2 internals FIFOs at init

The C2 TCAM has internal FIFOs that are only useful for the built-in
self-tests. Disable these FIFOS at init, as recommended in the
functionnal specs.
Suggested-by: default avatarAlan Winkowski <walan@marvell.com>
Signed-off-by: default avatarMaxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ae8e1d5e
...@@ -148,6 +148,8 @@ ...@@ -148,6 +148,8 @@
#define MVPP22_CLS_C2_ATTR2 0x1b6c #define MVPP22_CLS_C2_ATTR2 0x1b6c
#define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30) #define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30)
#define MVPP22_CLS_C2_ATTR3 0x1b70 #define MVPP22_CLS_C2_ATTR3 0x1b70
#define MVPP22_CLS_C2_TCAM_CTRL 0x1b90
#define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0)
/* Descriptor Manager Top Registers */ /* Descriptor Manager Top Registers */
#define MVPP2_RXQ_NUM_REG 0x2040 #define MVPP2_RXQ_NUM_REG 0x2040
......
...@@ -923,6 +923,12 @@ void mvpp2_cls_init(struct mvpp2 *priv) ...@@ -923,6 +923,12 @@ void mvpp2_cls_init(struct mvpp2 *priv)
mvpp2_cls_c2_write(priv, &c2); mvpp2_cls_c2_write(priv, &c2);
} }
/* Disable the FIFO stages in C2 engine, which are only used in BIST
* mode
*/
mvpp2_write(priv, MVPP22_CLS_C2_TCAM_CTRL,
MVPP22_CLS_C2_TCAM_BYPASS_FIFO);
mvpp2_cls_port_init_flows(priv); mvpp2_cls_port_init_flows(priv);
} }
......
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