Commit e8f055f0 authored by Nick Kossifidis's avatar Nick Kossifidis Committed by John W. Linville

ath5k: Update reset code

 * Update reset and sync with HALs

 * Clean up eeprom settings and tweaking of initvals and
   put them on separate functions

 * Set/Restore 32KHz ref clk operation

 * Add some more documentation

 TODO: Spur mitigation, tpc, half/quarter rate, compression etc

 v2: Address comments from Bob and Felix and fix RSSI threshold bug
 introduced on the first version of the patch
Signed-off-by: default avatarNick Kossifidis <mickflemm@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent a406c139
...@@ -222,6 +222,7 @@ ...@@ -222,6 +222,7 @@
#endif #endif
/* Initial values */ /* Initial values */
#define AR5K_INIT_CYCRSSI_THR1 2
#define AR5K_INIT_TX_LATENCY 502 #define AR5K_INIT_TX_LATENCY 502
#define AR5K_INIT_USEC 39 #define AR5K_INIT_USEC 39
#define AR5K_INIT_USEC_TURBO 79 #define AR5K_INIT_USEC_TURBO 79
...@@ -313,7 +314,7 @@ struct ath5k_srev_name { ...@@ -313,7 +314,7 @@ struct ath5k_srev_name {
#define AR5K_SREV_AR5424 0x90 /* Condor */ #define AR5K_SREV_AR5424 0x90 /* Condor */
#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
#define AR5K_SREV_AR5414 0xa0 /* Eagle */ #define AR5K_SREV_AR5414 0xa0 /* Eagle */
#define AR5K_SREV_AR2415 0xb0 /* Cobra */ #define AR5K_SREV_AR2415 0xb0 /* Talon */
#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
#define AR5K_SREV_AR5418 0xca /* PCI-E */ #define AR5K_SREV_AR5418 0xca /* PCI-E */
#define AR5K_SREV_AR2425 0xe0 /* Swan */ #define AR5K_SREV_AR2425 0xe0 /* Swan */
...@@ -331,7 +332,7 @@ struct ath5k_srev_name { ...@@ -331,7 +332,7 @@ struct ath5k_srev_name {
#define AR5K_SREV_RAD_2112B 0x46 #define AR5K_SREV_RAD_2112B 0x46
#define AR5K_SREV_RAD_2413 0x50 #define AR5K_SREV_RAD_2413 0x50
#define AR5K_SREV_RAD_5413 0x60 #define AR5K_SREV_RAD_5413 0x60
#define AR5K_SREV_RAD_2316 0x70 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
#define AR5K_SREV_RAD_2317 0x80 #define AR5K_SREV_RAD_2317 0x80
#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
#define AR5K_SREV_RAD_2425 0xa2 #define AR5K_SREV_RAD_2425 0xa2
...@@ -340,7 +341,7 @@ struct ath5k_srev_name { ...@@ -340,7 +341,7 @@ struct ath5k_srev_name {
#define AR5K_SREV_PHY_5211 0x30 #define AR5K_SREV_PHY_5211 0x30
#define AR5K_SREV_PHY_5212 0x41 #define AR5K_SREV_PHY_5212 0x41
#define AR5K_SREV_PHY_5212A 0x42 #define AR5K_SREV_PHY_5212A 0x42
#define AR5K_SREV_PHY_2112B 0x43 #define AR5K_SREV_PHY_5212B 0x43
#define AR5K_SREV_PHY_2413 0x45 #define AR5K_SREV_PHY_2413 0x45
#define AR5K_SREV_PHY_5413 0x61 #define AR5K_SREV_PHY_5413 0x61
#define AR5K_SREV_PHY_2425 0x70 #define AR5K_SREV_PHY_2425 0x70
...@@ -1030,7 +1031,6 @@ struct ath5k_hw { ...@@ -1030,7 +1031,6 @@ struct ath5k_hw {
u16 ah_phy_revision; u16 ah_phy_revision;
u16 ah_radio_5ghz_revision; u16 ah_radio_5ghz_revision;
u16 ah_radio_2ghz_revision; u16 ah_radio_2ghz_revision;
u32 ah_phy_spending;
enum ath5k_version ah_version; enum ath5k_version ah_version;
enum ath5k_radio ah_radio; enum ath5k_radio ah_radio;
...@@ -1156,6 +1156,7 @@ extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_l ...@@ -1156,6 +1156,7 @@ extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_l
/* EEPROM access functions */ /* EEPROM access functions */
extern int ath5k_eeprom_init(struct ath5k_hw *ah); extern int ath5k_eeprom_init(struct ath5k_hw *ah);
extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
/* Protocol Control Unit Functions */ /* Protocol Control Unit Functions */
extern int ath5k_hw_set_opmode(struct ath5k_hw *ah); extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
...@@ -1258,6 +1259,7 @@ extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power); ...@@ -1258,6 +1259,7 @@ extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
/* /*
* Translate usec to hw clock units * Translate usec to hw clock units
* TODO: Half/quarter rate
*/ */
static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
{ {
...@@ -1266,6 +1268,7 @@ static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) ...@@ -1266,6 +1268,7 @@ static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
/* /*
* Translate hw clock units to usec * Translate hw clock units to usec
* TODO: Half/quarter rate
*/ */
static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
{ {
......
...@@ -169,7 +169,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) ...@@ -169,7 +169,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
ah->ah_single_chip = false; ah->ah_single_chip = false;
ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
CHANNEL_2GHZ); CHANNEL_2GHZ);
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
break; break;
case AR5K_SREV_RAD_5112: case AR5K_SREV_RAD_5112:
case AR5K_SREV_RAD_2112: case AR5K_SREV_RAD_2112:
...@@ -177,38 +176,31 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) ...@@ -177,38 +176,31 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
ah->ah_single_chip = false; ah->ah_single_chip = false;
ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
CHANNEL_2GHZ); CHANNEL_2GHZ);
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
break; break;
case AR5K_SREV_RAD_2413: case AR5K_SREV_RAD_2413:
ah->ah_radio = AR5K_RF2413; ah->ah_radio = AR5K_RF2413;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
break; break;
case AR5K_SREV_RAD_5413: case AR5K_SREV_RAD_5413:
ah->ah_radio = AR5K_RF5413; ah->ah_radio = AR5K_RF5413;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
break; break;
case AR5K_SREV_RAD_2316: case AR5K_SREV_RAD_2316:
ah->ah_radio = AR5K_RF2316; ah->ah_radio = AR5K_RF2316;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
break; break;
case AR5K_SREV_RAD_2317: case AR5K_SREV_RAD_2317:
ah->ah_radio = AR5K_RF2317; ah->ah_radio = AR5K_RF2317;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2317;
break; break;
case AR5K_SREV_RAD_5424: case AR5K_SREV_RAD_5424:
if (ah->ah_mac_version == AR5K_SREV_AR2425 || if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
ah->ah_mac_version == AR5K_SREV_AR2417){ ah->ah_mac_version == AR5K_SREV_AR2417){
ah->ah_radio = AR5K_RF2425; ah->ah_radio = AR5K_RF2425;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
} else { } else {
ah->ah_radio = AR5K_RF5413; ah->ah_radio = AR5K_RF5413;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
} }
break; break;
default: default:
...@@ -227,29 +219,25 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) ...@@ -227,29 +219,25 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
ah->ah_radio = AR5K_RF2425; ah->ah_radio = AR5K_RF2425;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425; ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
} else if (srev == AR5K_SREV_AR5213A && } else if (srev == AR5K_SREV_AR5213A &&
ah->ah_phy_revision == AR5K_SREV_PHY_2112B) { ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
ah->ah_radio = AR5K_RF5112; ah->ah_radio = AR5K_RF5112;
ah->ah_single_chip = false; ah->ah_single_chip = false;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2112B; ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) { } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
ah->ah_radio = AR5K_RF2316; ah->ah_radio = AR5K_RF2316;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316; ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) || } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
ah->ah_phy_revision == AR5K_SREV_PHY_5413) { ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
ah->ah_radio = AR5K_RF5413; ah->ah_radio = AR5K_RF5413;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413; ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) || } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
ah->ah_phy_revision == AR5K_SREV_PHY_2413) { ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
ah->ah_radio = AR5K_RF2413; ah->ah_radio = AR5K_RF2413;
ah->ah_single_chip = true; ah->ah_single_chip = true;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413; ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
} else { } else {
ATH5K_ERR(sc, "Couldn't identify radio revision.\n"); ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
ret = -ENODEV; ret = -ENODEV;
......
...@@ -204,7 +204,7 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset, ...@@ -204,7 +204,7 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
/* Get antenna modes */ /* Get antenna modes */
ah->ah_antenna[mode][0] = ah->ah_antenna[mode][0] =
(ee->ee_ant_control[mode][0] << 4) | 0x1; (ee->ee_ant_control[mode][0] << 4);
ah->ah_antenna[mode][AR5K_ANT_FIXED_A] = ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
ee->ee_ant_control[mode][1] | ee->ee_ant_control[mode][1] |
(ee->ee_ant_control[mode][2] << 6) | (ee->ee_ant_control[mode][2] << 6) |
...@@ -1412,6 +1412,7 @@ ath5k_eeprom_init(struct ath5k_hw *ah) ...@@ -1412,6 +1412,7 @@ ath5k_eeprom_init(struct ath5k_hw *ah)
return 0; return 0;
} }
/* /*
* Read the MAC address from eeprom * Read the MAC address from eeprom
*/ */
...@@ -1448,3 +1449,14 @@ int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) ...@@ -1448,3 +1449,14 @@ int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
return 0; return 0;
} }
bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah)
{
u16 data;
ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data);
if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data)
return true;
else
return false;
}
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */ #define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
#define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */ #define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */
#define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */ #define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
......
...@@ -187,6 +187,7 @@ ...@@ -187,6 +187,7 @@
#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */
#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */ #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */ #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */
#define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */
#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */ #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */
/* /*
...@@ -753,7 +754,7 @@ ...@@ -753,7 +754,7 @@
*/ */
#define AR5K_DCU_SEQNUM_BASE 0x1140 #define AR5K_DCU_SEQNUM_BASE 0x1140
#define AR5K_DCU_SEQNUM_M 0x00000fff #define AR5K_DCU_SEQNUM_M 0x00000fff
#define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) #define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
/* /*
* DCU global IFS SIFS register * DCU global IFS SIFS register
...@@ -1467,7 +1468,7 @@ ...@@ -1467,7 +1468,7 @@
#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */ #define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */
#define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */ #define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */
#define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */ #define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */
#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* Test ARM (Adaptive Radio Mode ?) */ #define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */
/* /*
* Default antenna register [5211+] * Default antenna register [5211+]
...@@ -1679,7 +1680,7 @@ ...@@ -1679,7 +1680,7 @@
* TSF parameter register * TSF parameter register
*/ */
#define AR5K_TSF_PARM 0x8104 /* Register Address */ #define AR5K_TSF_PARM 0x8104 /* Register Address */
#define AR5K_TSF_PARM_INC_M 0x000000ff /* Mask for TSF increment */ #define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */
#define AR5K_TSF_PARM_INC_S 0 #define AR5K_TSF_PARM_INC_S 0
/* /*
...@@ -1691,7 +1692,7 @@ ...@@ -1691,7 +1692,7 @@
#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */ #define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */
#define AR5K_QOS_NOACK_BIT_OFFSET_S 4 #define AR5K_QOS_NOACK_BIT_OFFSET_S 4
#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */ #define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */
#define AR5K_QOS_NOACK_BYTE_OFFSET_S 8 #define AR5K_QOS_NOACK_BYTE_OFFSET_S 7
/* /*
* PHY error filter register * PHY error filter register
...@@ -1850,15 +1851,14 @@ ...@@ -1850,15 +1851,14 @@
* TST_2 (Misc config parameters) * TST_2 (Misc config parameters)
*/ */
#define AR5K_PHY_TST2 0x9800 /* Register Address */ #define AR5K_PHY_TST2 0x9800 /* Register Address */
#define AR5K_PHY_TST2_TRIG_SEL 0x00000001 /* Trigger select (?) (field ?) */ #define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/
#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) (field ?) */ #define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */
#define AR5K_PHY_TST2_CBUS_MODE 0x00000100 /* Cardbus mode (?) */ #define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */
/* bit reserved */
#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */ #define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */
#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */ #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */
#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */ #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */
#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */ #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */
#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch) */ #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */
#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */ #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */
#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */ #define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */
#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */ #define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */
...@@ -1928,8 +1928,8 @@ ...@@ -1928,8 +1928,8 @@
#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0 #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */ #define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */
#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* TX end to XLNA on */ #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */
#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 0 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8
#define AR5K_PHY_ADC_CTL 0x982c #define AR5K_PHY_ADC_CTL 0x982c
#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
...@@ -1963,7 +1963,7 @@ ...@@ -1963,7 +1963,7 @@
#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */ #define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */
#define AR5K_PHY_SETTLING_AGC_S 0 #define AR5K_PHY_SETTLING_AGC_S 0
#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */ #define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */
#define AR5K_PHY_SETTLINK_SWITCH_S 7 #define AR5K_PHY_SETTLING_SWITCH_S 7
/* /*
* PHY Gain registers * PHY Gain registers
...@@ -2069,14 +2069,14 @@ ...@@ -2069,14 +2069,14 @@
* PHY sleep registers [5112+] * PHY sleep registers [5112+]
*/ */
#define AR5K_PHY_SCR 0x9870 #define AR5K_PHY_SCR 0x9870
#define AR5K_PHY_SCR_32MHZ 0x0000001f
#define AR5K_PHY_SLMT 0x9874 #define AR5K_PHY_SLMT 0x9874
#define AR5K_PHY_SLMT_32MHZ 0x0000007f #define AR5K_PHY_SLMT_32MHZ 0x0000007f
#define AR5K_PHY_SCAL 0x9878 #define AR5K_PHY_SCAL 0x9878
#define AR5K_PHY_SCAL_32MHZ 0x0000000e #define AR5K_PHY_SCAL_32MHZ 0x0000000e
#define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a
#define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032
/* /*
* PHY PLL (Phase Locked Loop) control register * PHY PLL (Phase Locked Loop) control register
...@@ -2156,7 +2156,8 @@ ...@@ -2156,7 +2156,8 @@
#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */ #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */
#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */ #define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */
#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */ #define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */
#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x00000010 /* Switch table idle (?) */ #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */
#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4
/* /*
* PHY receiver delay register [5111+] * PHY receiver delay register [5111+]
...@@ -2196,7 +2197,7 @@ ...@@ -2196,7 +2197,7 @@
#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */ #define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */ #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */ #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 0 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */ #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */
#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */ #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */
#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */ #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */
...@@ -2278,6 +2279,15 @@ ...@@ -2278,6 +2279,15 @@
AR5K_PHY_FRAME_CTL_PARITY_ERR | \ AR5K_PHY_FRAME_CTL_PARITY_ERR | \
AR5K_PHY_FRAME_CTL_TIMING_ERR AR5K_PHY_FRAME_CTL_TIMING_ERR
/*
* PHY Tx Power adjustment register [5212A+]
*/
#define AR5K_PHY_TX_PWR_ADJ 0x994c
#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0
#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6
#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000
#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18
/* /*
* PHY radar detection register [5111+] * PHY radar detection register [5111+]
*/ */
...@@ -2331,7 +2341,7 @@ ...@@ -2331,7 +2341,7 @@
#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3 #define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00 #define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8 #define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ff3000 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
/* /*
...@@ -2459,17 +2469,7 @@ ...@@ -2459,17 +2469,7 @@
#define AR5K_PHY_SDELAY 0x99f4 #define AR5K_PHY_SDELAY 0x99f4
#define AR5K_PHY_SDELAY_32MHZ 0x000000ff #define AR5K_PHY_SDELAY_32MHZ 0x000000ff
#define AR5K_PHY_SPENDING 0x99f8 #define AR5K_PHY_SPENDING 0x99f8
#define AR5K_PHY_SPENDING_14 0x00000014
#define AR5K_PHY_SPENDING_18 0x00000018
#define AR5K_PHY_SPENDING_RF5111 0x00000018
#define AR5K_PHY_SPENDING_RF5112 0x00000014
/* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */
/* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */
#define AR5K_PHY_SPENDING_RF5413 0x00000018
#define AR5K_PHY_SPENDING_RF2413 0x00000018
#define AR5K_PHY_SPENDING_RF2316 0x00000018
#define AR5K_PHY_SPENDING_RF2317 0x00000018
#define AR5K_PHY_SPENDING_RF2425 0x00000014
/* /*
* PHY PAPD I (power?) table (?) * PHY PAPD I (power?) table (?)
......
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