Commit e9f9fe35 authored by Dinh Nguyen's avatar Dinh Nguyen

ARM: socfpga: dts: Fix gpio dts entry for the correct clock

The correct clock for the HPS gpio(s) should be the l4_mp_clk.
Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent c5dab6e2
...@@ -565,7 +565,7 @@ gpio0: gpio@ff708000 { ...@@ -565,7 +565,7 @@ gpio0: gpio@ff708000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "snps,dw-apb-gpio"; compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>; reg = <0xff708000 0x1000>;
clocks = <&per_base_clk>; clocks = <&l4_mp_clk>;
status = "disabled"; status = "disabled";
porta: gpio-controller@0 { porta: gpio-controller@0 {
...@@ -585,7 +585,7 @@ gpio1: gpio@ff709000 { ...@@ -585,7 +585,7 @@ gpio1: gpio@ff709000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "snps,dw-apb-gpio"; compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>; reg = <0xff709000 0x1000>;
clocks = <&per_base_clk>; clocks = <&l4_mp_clk>;
status = "disabled"; status = "disabled";
portb: gpio-controller@0 { portb: gpio-controller@0 {
...@@ -605,7 +605,7 @@ gpio2: gpio@ff70a000 { ...@@ -605,7 +605,7 @@ gpio2: gpio@ff70a000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "snps,dw-apb-gpio"; compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>; reg = <0xff70a000 0x1000>;
clocks = <&per_base_clk>; clocks = <&l4_mp_clk>;
status = "disabled"; status = "disabled";
portc: gpio-controller@0 { portc: gpio-controller@0 {
......
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