Commit ea20f117 authored by Andrew Jones's avatar Andrew Jones Committed by Palmer Dabbelt

dt-bindings: riscv: Document cboz-block-size

The Zicboz operation (cbo.zero) operates on a block-size defined
for the cpu-core. While we already have the riscv,cbom-block-size
property, it only provides the block size for Zicbom operations.
Even though it's likely Zicboz and Zicbom will use the same size,
that's not required by the specification. Create another property
specifically for Zicboz.

Cc: Rob Herring <robh@kernel.org>
Signed-off-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230224162631.405473-4-ajones@ventanamicro.comSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 8b05e7d0
...@@ -72,6 +72,11 @@ properties: ...@@ -72,6 +72,11 @@ properties:
description: description:
The blocksize in bytes for the Zicbom cache operations. The blocksize in bytes for the Zicbom cache operations.
riscv,cboz-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The blocksize in bytes for the Zicboz cache operations.
riscv,isa: riscv,isa:
description: description:
Identifies the specific RISC-V instruction set architecture Identifies the specific RISC-V instruction set architecture
......
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