Commit ead5f963 authored by Gilad Ben-Yossef's avatar Gilad Ben-Yossef Committed by Greg Kroah-Hartman

staging: ccree: fix typos

Fix a bunch of comment typos.
Signed-off-by: default avatarGilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f9f28469
...@@ -2481,7 +2481,7 @@ static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx, ...@@ -2481,7 +2481,7 @@ static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx,
* \param drvdata * \param drvdata
* \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256 * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256
* *
* \return u32 The address of the inital digest in SRAM * \return u32 The address of the initial digest in SRAM
*/ */
ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode) ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode)
{ {
......
...@@ -95,7 +95,7 @@ ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode); ...@@ -95,7 +95,7 @@ ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode);
* \param drvdata * \param drvdata
* \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512 * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
* *
* \return u32 The address of the inital digest in SRAM * \return u32 The address of the initial digest in SRAM
*/ */
ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode); ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode);
......
...@@ -198,7 +198,7 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata) ...@@ -198,7 +198,7 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata)
ivgen_ctx = drvdata->ivgen_handle; ivgen_ctx = drvdata->ivgen_handle;
/* Allocate pool's header for intial enc. key/IV */ /* Allocate pool's header for initial enc. key/IV */
ivgen_ctx->pool_meta = dma_alloc_coherent(device, SSI_IVPOOL_META_SIZE, ivgen_ctx->pool_meta = dma_alloc_coherent(device, SSI_IVPOOL_META_SIZE,
&ivgen_ctx->pool_meta_dma, &ivgen_ctx->pool_meta_dma,
GFP_KERNEL); GFP_KERNEL);
......
...@@ -205,7 +205,7 @@ static inline int request_mgr_queues_status_check( ...@@ -205,7 +205,7 @@ static inline int request_mgr_queues_status_check(
struct device *dev = drvdata_to_dev(drvdata); struct device *dev = drvdata_to_dev(drvdata);
/* SW queue is checked only once as it will not /* SW queue is checked only once as it will not
* be chaned during the poll becasue the spinlock_bh * be chaned during the poll because the spinlock_bh
* is held by the thread * is held by the thread
*/ */
if (unlikely(((req_mgr_h->req_queue_head + 1) & if (unlikely(((req_mgr_h->req_queue_head + 1) &
......
...@@ -36,7 +36,7 @@ int request_mgr_init(struct ssi_drvdata *drvdata); ...@@ -36,7 +36,7 @@ int request_mgr_init(struct ssi_drvdata *drvdata);
* If "false": this function adds a dummy descriptor completion * If "false": this function adds a dummy descriptor completion
* and waits upon completion signal. * and waits upon completion signal.
* *
* \return int Returns -EINPROGRESS if "is_dout=ture"; "0" if "is_dout=false" * \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false"
*/ */
int send_request( int send_request(
struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req,
......
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