Commit eb7f84e3 authored by Michal Kalderon's avatar Michal Kalderon Committed by Jason Gunthorpe

RDMA/qedr: Add EDPM max size to alloc ucontext response

User space should receive the maximum edpm size from kernel driver,
similar to other edpm/ldpm related limits.  Add an additional parameter to
the alloc_ucontext_resp structure for the edpm maximum size.

In addition, pass an indication from user-space to kernel
(and not just kernel to user) that the DPM sizes are supported.

This is for supporting backward-forward compatibility between driver and
lib for everything related to DPM transaction and limit sizes.

This should have been part of commit mentioned in Fixes tag.

Link: https://lore.kernel.org/r/20200707063100.3811-3-michal.kalderon@marvell.com
Fixes: 93a3d05f ("RDMA/qedr: Add kernel capability flags for dpm enabled mode")
Signed-off-by: default avatarAriel Elior <ariel.elior@marvell.com>
Signed-off-by: default avatarMichal Kalderon <michal.kalderon@marvell.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent bbe4f424
...@@ -320,9 +320,12 @@ int qedr_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata) ...@@ -320,9 +320,12 @@ int qedr_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata)
QEDR_DPM_TYPE_ROCE_LEGACY | QEDR_DPM_TYPE_ROCE_LEGACY |
QEDR_DPM_TYPE_ROCE_EDPM_MODE; QEDR_DPM_TYPE_ROCE_EDPM_MODE;
uresp.dpm_flags |= QEDR_DPM_SIZES_SET; if (ureq.context_flags & QEDR_SUPPORT_DPM_SIZES) {
uresp.ldpm_limit_size = QEDR_LDPM_MAX_SIZE; uresp.dpm_flags |= QEDR_DPM_SIZES_SET;
uresp.edpm_trans_size = QEDR_EDPM_TRANS_SIZE; uresp.ldpm_limit_size = QEDR_LDPM_MAX_SIZE;
uresp.edpm_trans_size = QEDR_EDPM_TRANS_SIZE;
uresp.edpm_limit_size = QEDR_EDPM_MAX_SIZE;
}
uresp.wids_enabled = 1; uresp.wids_enabled = 1;
uresp.wid_count = oparams.wid_count; uresp.wid_count = oparams.wid_count;
......
...@@ -40,7 +40,8 @@ ...@@ -40,7 +40,8 @@
/* user kernel communication data structures. */ /* user kernel communication data structures. */
enum qedr_alloc_ucontext_flags { enum qedr_alloc_ucontext_flags {
QEDR_ALLOC_UCTX_EDPM_MODE = 1 << 0, QEDR_ALLOC_UCTX_EDPM_MODE = 1 << 0,
QEDR_ALLOC_UCTX_DB_REC = 1 << 1 QEDR_ALLOC_UCTX_DB_REC = 1 << 1,
QEDR_SUPPORT_DPM_SIZES = 1 << 2,
}; };
struct qedr_alloc_ucontext_req { struct qedr_alloc_ucontext_req {
...@@ -50,6 +51,7 @@ struct qedr_alloc_ucontext_req { ...@@ -50,6 +51,7 @@ struct qedr_alloc_ucontext_req {
#define QEDR_LDPM_MAX_SIZE (8192) #define QEDR_LDPM_MAX_SIZE (8192)
#define QEDR_EDPM_TRANS_SIZE (64) #define QEDR_EDPM_TRANS_SIZE (64)
#define QEDR_EDPM_MAX_SIZE (ROCE_REQ_MAX_INLINE_DATA_SIZE)
enum qedr_rdma_dpm_type { enum qedr_rdma_dpm_type {
QEDR_DPM_TYPE_NONE = 0, QEDR_DPM_TYPE_NONE = 0,
...@@ -77,6 +79,8 @@ struct qedr_alloc_ucontext_resp { ...@@ -77,6 +79,8 @@ struct qedr_alloc_ucontext_resp {
__u16 ldpm_limit_size; __u16 ldpm_limit_size;
__u8 edpm_trans_size; __u8 edpm_trans_size;
__u8 reserved; __u8 reserved;
__u16 edpm_limit_size;
__u8 padding[6];
}; };
struct qedr_alloc_pd_ureq { struct qedr_alloc_pd_ureq {
......
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