Commit ebb69c95 authored by Clint Taylor's avatar Clint Taylor Committed by Daniel Vetter

drm/i915: Enable pixel replicated modes on BDW and HSW.

Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing
to the DPLL only double the pixel clock.

ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel)
ver3: Do not set pixel multiplier if transcoder is eDP (Ville)
ver4: Macro name change to PIPE_MULT and default else pixel_multiplier

Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarClint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Appease checkpatch and move one hunk back into the right
place that git am misplace!?]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 67956867
...@@ -2443,6 +2443,7 @@ enum punit_power_well { ...@@ -2443,6 +2443,7 @@ enum punit_power_well {
#define _PIPEASRC 0x6001c #define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020 #define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028 #define _VSYNCSHIFT_A 0x60028
#define _PIPE_MULT_A 0x6002c
/* Pipe B timing regs */ /* Pipe B timing regs */
#define _HTOTAL_B 0x61000 #define _HTOTAL_B 0x61000
...@@ -2454,6 +2455,7 @@ enum punit_power_well { ...@@ -2454,6 +2455,7 @@ enum punit_power_well {
#define _PIPEBSRC 0x6101c #define _PIPEBSRC 0x6101c
#define _BCLRPAT_B 0x61020 #define _BCLRPAT_B 0x61020
#define _VSYNCSHIFT_B 0x61028 #define _VSYNCSHIFT_B 0x61028
#define _PIPE_MULT_B 0x6102c
#define TRANSCODER_A_OFFSET 0x60000 #define TRANSCODER_A_OFFSET 0x60000
#define TRANSCODER_B_OFFSET 0x61000 #define TRANSCODER_B_OFFSET 0x61000
...@@ -2474,6 +2476,7 @@ enum punit_power_well { ...@@ -2474,6 +2476,7 @@ enum punit_power_well {
#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
/* HSW+ eDP PSR registers */ /* HSW+ eDP PSR registers */
#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
......
...@@ -4222,6 +4222,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) ...@@ -4222,6 +4222,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_set_pipe_timings(intel_crtc); intel_set_pipe_timings(intel_crtc);
if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
intel_crtc->config.pixel_multiplier - 1);
}
if (intel_crtc->config.has_pch_encoder) { if (intel_crtc->config.has_pch_encoder) {
intel_cpu_transcoder_set_m_n(intel_crtc, intel_cpu_transcoder_set_m_n(intel_crtc,
&intel_crtc->config.fdi_m_n, NULL); &intel_crtc->config.fdi_m_n, NULL);
...@@ -7890,7 +7895,12 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, ...@@ -7890,7 +7895,12 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
(I915_READ(IPS_CTL) & IPS_ENABLE); (I915_READ(IPS_CTL) & IPS_ENABLE);
pipe_config->pixel_multiplier = 1; if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
pipe_config->pixel_multiplier =
I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
} else {
pipe_config->pixel_multiplier = 1;
}
return true; return true;
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment