Commit ebc7a496 authored by Kalle Valo's avatar Kalle Valo

Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git

ath.git patches for v5.19. Major changes:

ath11k

* Wake-on-WLAN support for QCA6390 and WCN6855

* device recovery (firmware restart) support for QCA6390 and WCN6855

wcn36xx

* support for transmit rate reporting to user space
parents 26bb9340 b9e34ba6
...@@ -728,20 +728,17 @@ static int ath10k_ahb_probe(struct platform_device *pdev) ...@@ -728,20 +728,17 @@ static int ath10k_ahb_probe(struct platform_device *pdev)
struct ath10k *ar; struct ath10k *ar;
struct ath10k_ahb *ar_ahb; struct ath10k_ahb *ar_ahb;
struct ath10k_pci *ar_pci; struct ath10k_pci *ar_pci;
const struct of_device_id *of_id;
enum ath10k_hw_rev hw_rev; enum ath10k_hw_rev hw_rev;
size_t size; size_t size;
int ret; int ret;
struct ath10k_bus_params bus_params = {}; struct ath10k_bus_params bus_params = {};
of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev); hw_rev = (enum ath10k_hw_rev)of_device_get_match_data(&pdev->dev);
if (!of_id) { if (!hw_rev) {
dev_err(&pdev->dev, "failed to find matching device tree id\n"); dev_err(&pdev->dev, "OF data missing\n");
return -EINVAL; return -EINVAL;
} }
hw_rev = (enum ath10k_hw_rev)of_id->data;
size = sizeof(*ar_pci) + sizeof(*ar_ahb); size = sizeof(*ar_pci) + sizeof(*ar_ahb);
ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB,
hw_rev, &ath10k_ahb_hif_ops); hw_rev, &ath10k_ahb_hif_ops);
......
...@@ -94,6 +94,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -94,6 +94,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = true, .tx_stats_over_pktlog = true,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA988X_HW_2_0_VERSION, .id = QCA988X_HW_2_0_VERSION,
...@@ -131,6 +132,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -131,6 +132,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = true, .tx_stats_over_pktlog = true,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA9887_HW_1_0_VERSION, .id = QCA9887_HW_1_0_VERSION,
...@@ -169,6 +171,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -169,6 +171,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA6174_HW_3_2_VERSION, .id = QCA6174_HW_3_2_VERSION,
...@@ -202,6 +205,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -202,6 +205,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.bmi_large_size_download = true, .bmi_large_size_download = true,
.supports_peer_stats_info = true, .supports_peer_stats_info = true,
.dynamic_sar_support = true, .dynamic_sar_support = true,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA6174_HW_2_1_VERSION, .id = QCA6174_HW_2_1_VERSION,
...@@ -239,6 +243,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -239,6 +243,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA6174_HW_2_1_VERSION, .id = QCA6174_HW_2_1_VERSION,
...@@ -276,6 +281,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -276,6 +281,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA6174_HW_3_0_VERSION, .id = QCA6174_HW_3_0_VERSION,
...@@ -313,6 +319,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -313,6 +319,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA6174_HW_3_2_VERSION, .id = QCA6174_HW_3_2_VERSION,
...@@ -354,6 +361,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -354,6 +361,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.supports_peer_stats_info = true, .supports_peer_stats_info = true,
.dynamic_sar_support = true, .dynamic_sar_support = true,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA99X0_HW_2_0_DEV_VERSION, .id = QCA99X0_HW_2_0_DEV_VERSION,
...@@ -397,6 +405,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -397,6 +405,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA9984_HW_1_0_DEV_VERSION, .id = QCA9984_HW_1_0_DEV_VERSION,
...@@ -447,6 +456,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -447,6 +456,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA9888_HW_2_0_DEV_VERSION, .id = QCA9888_HW_2_0_DEV_VERSION,
...@@ -494,6 +504,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -494,6 +504,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA9377_HW_1_0_DEV_VERSION, .id = QCA9377_HW_1_0_DEV_VERSION,
...@@ -531,6 +542,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -531,6 +542,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA9377_HW_1_1_DEV_VERSION, .id = QCA9377_HW_1_1_DEV_VERSION,
...@@ -570,6 +582,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -570,6 +582,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA9377_HW_1_1_DEV_VERSION, .id = QCA9377_HW_1_1_DEV_VERSION,
...@@ -600,6 +613,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -600,6 +613,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.uart_pin_workaround = true, .uart_pin_workaround = true,
.credit_size_workaround = true, .credit_size_workaround = true,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = QCA4019_HW_1_0_DEV_VERSION, .id = QCA4019_HW_1_0_DEV_VERSION,
...@@ -644,6 +658,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -644,6 +658,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = false, .dynamic_sar_support = false,
.hw_restart_disconnect = false,
}, },
{ {
.id = WCN3990_HW_1_0_DEV_VERSION, .id = WCN3990_HW_1_0_DEV_VERSION,
...@@ -674,6 +689,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -674,6 +689,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.credit_size_workaround = false, .credit_size_workaround = false,
.tx_stats_over_pktlog = false, .tx_stats_over_pktlog = false,
.dynamic_sar_support = true, .dynamic_sar_support = true,
.hw_restart_disconnect = true,
}, },
}; };
...@@ -2442,6 +2458,7 @@ EXPORT_SYMBOL(ath10k_core_napi_sync_disable); ...@@ -2442,6 +2458,7 @@ EXPORT_SYMBOL(ath10k_core_napi_sync_disable);
static void ath10k_core_restart(struct work_struct *work) static void ath10k_core_restart(struct work_struct *work)
{ {
struct ath10k *ar = container_of(work, struct ath10k, restart_work); struct ath10k *ar = container_of(work, struct ath10k, restart_work);
struct ath10k_vif *arvif;
int ret; int ret;
set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
...@@ -2480,6 +2497,14 @@ static void ath10k_core_restart(struct work_struct *work) ...@@ -2480,6 +2497,14 @@ static void ath10k_core_restart(struct work_struct *work)
ar->state = ATH10K_STATE_RESTARTING; ar->state = ATH10K_STATE_RESTARTING;
ath10k_halt(ar); ath10k_halt(ar);
ath10k_scan_finish(ar); ath10k_scan_finish(ar);
if (ar->hw_params.hw_restart_disconnect) {
list_for_each_entry(arvif, &ar->arvifs, list) {
if (arvif->is_up &&
arvif->vdev_type == WMI_VDEV_TYPE_STA)
ieee80211_hw_restart_disconnect(arvif->vif);
}
}
ieee80211_restart_hw(ar->hw); ieee80211_restart_hw(ar->hw);
break; break;
case ATH10K_STATE_OFF: case ATH10K_STATE_OFF:
......
...@@ -633,6 +633,8 @@ struct ath10k_hw_params { ...@@ -633,6 +633,8 @@ struct ath10k_hw_params {
bool supports_peer_stats_info; bool supports_peer_stats_info;
bool dynamic_sar_support; bool dynamic_sar_support;
bool hw_restart_disconnect;
}; };
struct htt_resp; struct htt_resp;
......
...@@ -345,6 +345,12 @@ static void ath10k_usb_rx_complete(struct ath10k *ar, struct sk_buff *skb) ...@@ -345,6 +345,12 @@ static void ath10k_usb_rx_complete(struct ath10k *ar, struct sk_buff *skb)
ep->ep_ops.ep_rx_complete(ar, skb); ep->ep_ops.ep_rx_complete(ar, skb);
/* The RX complete handler now owns the skb... */ /* The RX complete handler now owns the skb... */
if (test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) {
local_bh_disable();
napi_schedule(&ar->napi);
local_bh_enable();
}
return; return;
out_free_skb: out_free_skb:
...@@ -387,6 +393,7 @@ static int ath10k_usb_hif_start(struct ath10k *ar) ...@@ -387,6 +393,7 @@ static int ath10k_usb_hif_start(struct ath10k *ar)
int i; int i;
struct ath10k_usb *ar_usb = ath10k_usb_priv(ar); struct ath10k_usb *ar_usb = ath10k_usb_priv(ar);
ath10k_core_napi_enable(ar);
ath10k_usb_start_recv_pipes(ar); ath10k_usb_start_recv_pipes(ar);
/* set the TX resource avail threshold for each TX pipe */ /* set the TX resource avail threshold for each TX pipe */
...@@ -462,6 +469,7 @@ static int ath10k_usb_hif_tx_sg(struct ath10k *ar, u8 pipe_id, ...@@ -462,6 +469,7 @@ static int ath10k_usb_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
static void ath10k_usb_hif_stop(struct ath10k *ar) static void ath10k_usb_hif_stop(struct ath10k *ar)
{ {
ath10k_usb_flush_all(ar); ath10k_usb_flush_all(ar);
ath10k_core_napi_sync_disable(ar);
} }
static u16 ath10k_usb_hif_get_free_queue_number(struct ath10k *ar, u8 pipe_id) static u16 ath10k_usb_hif_get_free_queue_number(struct ath10k *ar, u8 pipe_id)
...@@ -966,6 +974,20 @@ static int ath10k_usb_create(struct ath10k *ar, ...@@ -966,6 +974,20 @@ static int ath10k_usb_create(struct ath10k *ar,
return ret; return ret;
} }
static int ath10k_usb_napi_poll(struct napi_struct *ctx, int budget)
{
struct ath10k *ar = container_of(ctx, struct ath10k, napi);
int done;
done = ath10k_htt_rx_hl_indication(ar, budget);
ath10k_dbg(ar, ATH10K_DBG_USB, "napi poll: done: %d, budget:%d\n", done, budget);
if (done < budget)
napi_complete_done(ctx, done);
return done;
}
/* ath10k usb driver registered functions */ /* ath10k usb driver registered functions */
static int ath10k_usb_probe(struct usb_interface *interface, static int ath10k_usb_probe(struct usb_interface *interface,
const struct usb_device_id *id) const struct usb_device_id *id)
...@@ -992,6 +1014,9 @@ static int ath10k_usb_probe(struct usb_interface *interface, ...@@ -992,6 +1014,9 @@ static int ath10k_usb_probe(struct usb_interface *interface,
return -ENOMEM; return -ENOMEM;
} }
netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_usb_napi_poll,
ATH10K_NAPI_BUDGET);
usb_get_dev(dev); usb_get_dev(dev);
vendor_id = le16_to_cpu(dev->descriptor.idVendor); vendor_id = le16_to_cpu(dev->descriptor.idVendor);
product_id = le16_to_cpu(dev->descriptor.idProduct); product_id = le16_to_cpu(dev->descriptor.idProduct);
...@@ -1013,6 +1038,7 @@ static int ath10k_usb_probe(struct usb_interface *interface, ...@@ -1013,6 +1038,7 @@ static int ath10k_usb_probe(struct usb_interface *interface,
bus_params.dev_type = ATH10K_DEV_TYPE_HL; bus_params.dev_type = ATH10K_DEV_TYPE_HL;
/* TODO: don't know yet how to get chip_id with USB */ /* TODO: don't know yet how to get chip_id with USB */
bus_params.chip_id = 0; bus_params.chip_id = 0;
bus_params.hl_msdu_ids = true;
ret = ath10k_core_register(ar, &bus_params); ret = ath10k_core_register(ar, &bus_params);
if (ret) { if (ret) {
ath10k_warn(ar, "failed to register driver core: %d\n", ret); ath10k_warn(ar, "failed to register driver core: %d\n", ret);
...@@ -1044,6 +1070,7 @@ static void ath10k_usb_remove(struct usb_interface *interface) ...@@ -1044,6 +1070,7 @@ static void ath10k_usb_remove(struct usb_interface *interface)
return; return;
ath10k_core_unregister(ar_usb->ar); ath10k_core_unregister(ar_usb->ar);
netif_napi_del(&ar_usb->ar->napi);
ath10k_usb_destroy(ar_usb->ar); ath10k_usb_destroy(ar_usb->ar);
usb_put_dev(interface_to_usbdev(interface)); usb_put_dev(interface_to_usbdev(interface));
ath10k_core_destroy(ar_usb->ar); ath10k_core_destroy(ar_usb->ar);
......
...@@ -16,20 +16,20 @@ ath11k-y += core.o \ ...@@ -16,20 +16,20 @@ ath11k-y += core.o \
ce.o \ ce.o \
peer.o \ peer.o \
dbring.o \ dbring.o \
hw.o \ hw.o
wow.o
ath11k-$(CONFIG_ATH11K_DEBUGFS) += debugfs.o debugfs_htt_stats.o debugfs_sta.o ath11k-$(CONFIG_ATH11K_DEBUGFS) += debugfs.o debugfs_htt_stats.o debugfs_sta.o
ath11k-$(CONFIG_NL80211_TESTMODE) += testmode.o ath11k-$(CONFIG_NL80211_TESTMODE) += testmode.o
ath11k-$(CONFIG_ATH11K_TRACING) += trace.o ath11k-$(CONFIG_ATH11K_TRACING) += trace.o
ath11k-$(CONFIG_THERMAL) += thermal.o ath11k-$(CONFIG_THERMAL) += thermal.o
ath11k-$(CONFIG_ATH11K_SPECTRAL) += spectral.o ath11k-$(CONFIG_ATH11K_SPECTRAL) += spectral.o
ath11k-$(CONFIG_PM) += wow.o
obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o
ath11k_ahb-y += ahb.o ath11k_ahb-y += ahb.o
obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o
ath11k_pci-y += mhi.o pci.o ath11k_pci-y += mhi.o pci.o pcic.o
# for tracing framework to find trace.h # for tracing framework to find trace.h
CFLAGS_trace.o := -I$(src) CFLAGS_trace.o := -I$(src)
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/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* SPDX-License-Identifier: BSD-3-Clause-Clear */
/* /*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef ATH11K_CORE_H #ifndef ATH11K_CORE_H
...@@ -10,6 +11,9 @@ ...@@ -10,6 +11,9 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/bitfield.h> #include <linux/bitfield.h>
#include <linux/dmi.h>
#include <linux/ctype.h>
#include <linux/rhashtable.h>
#include "qmi.h" #include "qmi.h"
#include "htc.h" #include "htc.h"
#include "wmi.h" #include "wmi.h"
...@@ -23,6 +27,7 @@ ...@@ -23,6 +27,7 @@
#include "thermal.h" #include "thermal.h"
#include "dbring.h" #include "dbring.h"
#include "spectral.h" #include "spectral.h"
#include "wow.h"
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
...@@ -36,9 +41,26 @@ ...@@ -36,9 +41,26 @@
#define ATH11K_INVALID_HW_MAC_ID 0xFF #define ATH11K_INVALID_HW_MAC_ID 0xFF
#define ATH11K_CONNECTION_LOSS_HZ (3 * HZ) #define ATH11K_CONNECTION_LOSS_HZ (3 * HZ)
/* SMBIOS type containing Board Data File Name Extension */
#define ATH11K_SMBIOS_BDF_EXT_TYPE 0xF8
/* SMBIOS type structure length (excluding strings-set) */
#define ATH11K_SMBIOS_BDF_EXT_LENGTH 0x9
/* The magic used by QCA spec */
#define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_"
extern unsigned int ath11k_frame_mode; extern unsigned int ath11k_frame_mode;
#define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ)
#define ATH11K_MON_TIMER_INTERVAL 10 #define ATH11K_MON_TIMER_INTERVAL 10
#define ATH11K_RESET_TIMEOUT_HZ (20 * HZ)
#define ATH11K_RESET_MAX_FAIL_COUNT_FIRST 3
#define ATH11K_RESET_MAX_FAIL_COUNT_FINAL 5
#define ATH11K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
#define ATH11K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
#define ATH11K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
enum ath11k_supported_bw { enum ath11k_supported_bw {
ATH11K_BW_20 = 0, ATH11K_BW_20 = 0,
...@@ -147,6 +169,13 @@ struct ath11k_ext_irq_grp { ...@@ -147,6 +169,13 @@ struct ath11k_ext_irq_grp {
struct net_device napi_ndev; struct net_device napi_ndev;
}; };
struct ath11k_smbios_bdf {
struct dmi_header hdr;
u32 padding;
u8 bdf_enabled;
u8 bdf_ext[];
};
#define HEHANDLE_CAP_PHYINFO_SIZE 3 #define HEHANDLE_CAP_PHYINFO_SIZE 3
#define HECAP_PHYINFO_SIZE 9 #define HECAP_PHYINFO_SIZE 9
#define HECAP_MACINFO_SIZE 5 #define HECAP_MACINFO_SIZE 5
...@@ -189,6 +218,12 @@ enum ath11k_scan_state { ...@@ -189,6 +218,12 @@ enum ath11k_scan_state {
ATH11K_SCAN_ABORTING, ATH11K_SCAN_ABORTING,
}; };
enum ath11k_11d_state {
ATH11K_11D_IDLE,
ATH11K_11D_PREPARING,
ATH11K_11D_RUNNING,
};
enum ath11k_dev_flags { enum ath11k_dev_flags {
ATH11K_CAC_RUNNING, ATH11K_CAC_RUNNING,
ATH11K_FLAG_CORE_REGISTERED, ATH11K_FLAG_CORE_REGISTERED,
...@@ -204,6 +239,8 @@ enum ath11k_dev_flags { ...@@ -204,6 +239,8 @@ enum ath11k_dev_flags {
ATH11K_FLAG_CE_IRQ_ENABLED, ATH11K_FLAG_CE_IRQ_ENABLED,
ATH11K_FLAG_EXT_IRQ_ENABLED, ATH11K_FLAG_EXT_IRQ_ENABLED,
ATH11K_FLAG_FIXED_MEM_RGN, ATH11K_FLAG_FIXED_MEM_RGN,
ATH11K_FLAG_DEVICE_INIT_DONE,
ATH11K_FLAG_MULTI_MSI_VECTORS,
}; };
enum ath11k_monitor_flags { enum ath11k_monitor_flags {
...@@ -212,6 +249,30 @@ enum ath11k_monitor_flags { ...@@ -212,6 +249,30 @@ enum ath11k_monitor_flags {
ATH11K_FLAG_MONITOR_VDEV_CREATED, ATH11K_FLAG_MONITOR_VDEV_CREATED,
}; };
#define ATH11K_IPV6_UC_TYPE 0
#define ATH11K_IPV6_AC_TYPE 1
#define ATH11K_IPV6_MAX_COUNT 16
#define ATH11K_IPV4_MAX_COUNT 2
struct ath11k_arp_ns_offload {
u8 ipv4_addr[ATH11K_IPV4_MAX_COUNT][4];
u32 ipv4_count;
u32 ipv6_count;
u8 ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
u8 self_ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
u8 ipv6_type[ATH11K_IPV6_MAX_COUNT];
bool ipv6_valid[ATH11K_IPV6_MAX_COUNT];
u8 mac_addr[ETH_ALEN];
};
struct ath11k_rekey_data {
u8 kck[NL80211_KCK_LEN];
u8 kek[NL80211_KCK_LEN];
u64 replay_ctr;
bool enable_offload;
};
struct ath11k_vif { struct ath11k_vif {
u32 vdev_id; u32 vdev_id;
enum wmi_vdev_type vdev_type; enum wmi_vdev_type vdev_type;
...@@ -263,6 +324,9 @@ struct ath11k_vif { ...@@ -263,6 +324,9 @@ struct ath11k_vif {
bool bcca_zero_sent; bool bcca_zero_sent;
bool do_not_send_tmpl; bool do_not_send_tmpl;
struct ieee80211_chanctx_conf chanctx; struct ieee80211_chanctx_conf chanctx;
struct ath11k_arp_ns_offload arp_ns_offload;
struct ath11k_rekey_data rekey_data;
#ifdef CONFIG_ATH11K_DEBUGFS #ifdef CONFIG_ATH11K_DEBUGFS
struct dentry *debugfs_twt; struct dentry *debugfs_twt;
#endif /* CONFIG_ATH11K_DEBUGFS */ #endif /* CONFIG_ATH11K_DEBUGFS */
...@@ -590,6 +654,9 @@ struct ath11k { ...@@ -590,6 +654,9 @@ struct ath11k {
struct work_struct wmi_mgmt_tx_work; struct work_struct wmi_mgmt_tx_work;
struct sk_buff_head wmi_mgmt_tx_queue; struct sk_buff_head wmi_mgmt_tx_queue;
struct ath11k_wow wow;
struct completion target_suspend;
bool target_suspend_ack;
struct ath11k_per_peer_tx_stats peer_tx_stats; struct ath11k_per_peer_tx_stats peer_tx_stats;
struct list_head ppdu_stats_info; struct list_head ppdu_stats_info;
u32 ppdu_stat_list_depth; u32 ppdu_stat_list_depth;
...@@ -607,12 +674,13 @@ struct ath11k { ...@@ -607,12 +674,13 @@ struct ath11k {
bool dfs_block_radar_events; bool dfs_block_radar_events;
struct ath11k_thermal thermal; struct ath11k_thermal thermal;
u32 vdev_id_11d_scan; u32 vdev_id_11d_scan;
struct completion finish_11d_scan; struct completion completed_11d_scan;
struct completion finish_11d_ch_list; enum ath11k_11d_state state_11d;
bool pending_11d;
bool regdom_set_by_user; bool regdom_set_by_user;
int hw_rate_code; int hw_rate_code;
u8 twt_enabled; u8 twt_enabled;
bool nlo_enabled;
u8 alpha2[REG_ALPHA2_LEN + 1];
}; };
struct ath11k_band_cap { struct ath11k_band_cap {
...@@ -662,6 +730,14 @@ struct ath11k_bus_params { ...@@ -662,6 +730,14 @@ struct ath11k_bus_params {
bool static_window_map; bool static_window_map;
}; };
struct ath11k_pci_ops {
int (*wakeup)(struct ath11k_base *ab);
void (*release)(struct ath11k_base *ab);
int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
};
/* IPQ8074 HW channel counters frequency value in hertz */ /* IPQ8074 HW channel counters frequency value in hertz */
#define IPQ8074_CC_FREQ_HERTZ 320000 #define IPQ8074_CC_FREQ_HERTZ 320000
...@@ -703,6 +779,19 @@ struct ath11k_soc_dp_stats { ...@@ -703,6 +779,19 @@ struct ath11k_soc_dp_stats {
struct ath11k_dp_ring_bp_stats bp_stats; struct ath11k_dp_ring_bp_stats bp_stats;
}; };
struct ath11k_msi_user {
char *name;
int num_vectors;
u32 base_vector;
};
struct ath11k_msi_config {
int total_vectors;
int total_users;
struct ath11k_msi_user *users;
u16 hw_rev;
};
/* Master structure to hold the hw data which may be used in core module */ /* Master structure to hold the hw data which may be used in core module */
struct ath11k_base { struct ath11k_base {
enum ath11k_hw_rev hw_rev; enum ath11k_hw_rev hw_rev;
...@@ -747,6 +836,18 @@ struct ath11k_base { ...@@ -747,6 +836,18 @@ struct ath11k_base {
struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS]; struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS];
struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS]; struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
unsigned long long free_vdev_map; unsigned long long free_vdev_map;
/* To synchronize rhash tbl write operation */
struct mutex tbl_mtx_lock;
/* The rhashtable containing struct ath11k_peer keyed by mac addr */
struct rhashtable *rhead_peer_addr;
struct rhashtable_params rhash_peer_addr_param;
/* The rhashtable containing struct ath11k_peer keyed by id */
struct rhashtable *rhead_peer_id;
struct rhashtable_params rhash_peer_id_param;
struct list_head peers; struct list_head peers;
wait_queue_head_t peer_mapping_wq; wait_queue_head_t peer_mapping_wq;
u8 mac_addr[ETH_ALEN]; u8 mac_addr[ETH_ALEN];
...@@ -788,6 +889,18 @@ struct ath11k_base { ...@@ -788,6 +889,18 @@ struct ath11k_base {
struct work_struct restart_work; struct work_struct restart_work;
struct work_struct update_11d_work; struct work_struct update_11d_work;
u8 new_alpha2[3]; u8 new_alpha2[3];
struct workqueue_struct *workqueue_aux;
struct work_struct reset_work;
atomic_t reset_count;
atomic_t recovery_count;
atomic_t recovery_start_count;
bool is_reset;
struct completion reset_complete;
struct completion reconfigure_complete;
struct completion recovery_start;
/* continuous recovery fail count */
atomic_t fail_cont_count;
unsigned long reset_fail_timeout;
struct { struct {
/* protected by data_lock */ /* protected by data_lock */
u32 fw_crash_counter; u32 fw_crash_counter;
...@@ -815,6 +928,17 @@ struct ath11k_base { ...@@ -815,6 +928,17 @@ struct ath11k_base {
u32 subsystem_device; u32 subsystem_device;
} id; } id;
struct {
struct {
const struct ath11k_msi_config *config;
u32 ep_base_data;
u32 addr_lo;
u32 addr_hi;
} msi;
const struct ath11k_pci_ops *ops;
} pci;
/* must be last */ /* must be last */
u8 drv_priv[] __aligned(sizeof(void *)); u8 drv_priv[] __aligned(sizeof(void *));
}; };
...@@ -996,7 +1120,7 @@ int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, ...@@ -996,7 +1120,7 @@ int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
const char *name); const char *name);
void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd); void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd);
int ath11k_core_check_dt(struct ath11k_base *ath11k); int ath11k_core_check_dt(struct ath11k_base *ath11k);
int ath11k_core_check_smbios(struct ath11k_base *ab);
void ath11k_core_halt(struct ath11k *ar); void ath11k_core_halt(struct ath11k *ar);
int ath11k_core_resume(struct ath11k_base *ab); int ath11k_core_resume(struct ath11k_base *ab);
int ath11k_core_suspend(struct ath11k_base *ab); int ath11k_core_suspend(struct ath11k_base *ab);
......
...@@ -596,6 +596,10 @@ static ssize_t ath11k_write_simulate_fw_crash(struct file *file, ...@@ -596,6 +596,10 @@ static ssize_t ath11k_write_simulate_fw_crash(struct file *file,
ret = ath11k_wmi_force_fw_hang_cmd(ar, ret = ath11k_wmi_force_fw_hang_cmd(ar,
ATH11K_WMI_FW_HANG_ASSERT_TYPE, ATH11K_WMI_FW_HANG_ASSERT_TYPE,
ATH11K_WMI_FW_HANG_DELAY); ATH11K_WMI_FW_HANG_DELAY);
} else if (!strcmp(buf, "hw-restart")) {
ath11k_info(ab, "user requested hw restart\n");
queue_work(ab->workqueue_aux, &ab->reset_work);
ret = 0;
} else { } else {
ret = -EINVAL; ret = -EINVAL;
goto exit; goto exit;
......
...@@ -272,6 +272,11 @@ void ath11k_htc_tx_completion_handler(struct ath11k_base *ab, ...@@ -272,6 +272,11 @@ void ath11k_htc_tx_completion_handler(struct ath11k_base *ab,
ep_tx_complete(htc->ab, skb); ep_tx_complete(htc->ab, skb);
} }
static void ath11k_htc_wakeup_from_suspend(struct ath11k_base *ab)
{
ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot wakeup from suspend is received\n");
}
void ath11k_htc_rx_completion_handler(struct ath11k_base *ab, void ath11k_htc_rx_completion_handler(struct ath11k_base *ab,
struct sk_buff *skb) struct sk_buff *skb)
{ {
...@@ -376,6 +381,7 @@ void ath11k_htc_rx_completion_handler(struct ath11k_base *ab, ...@@ -376,6 +381,7 @@ void ath11k_htc_rx_completion_handler(struct ath11k_base *ab,
ath11k_htc_suspend_complete(ab, false); ath11k_htc_suspend_complete(ab, false);
break; break;
case ATH11K_HTC_MSG_WAKEUP_FROM_SUSPEND_ID: case ATH11K_HTC_MSG_WAKEUP_FROM_SUSPEND_ID:
ath11k_htc_wakeup_from_suspend(ab);
break; break;
default: default:
ath11k_warn(ab, "ignoring unsolicited htc ep0 event %ld\n", ath11k_warn(ab, "ignoring unsolicited htc ep0 event %ld\n",
......
/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* SPDX-License-Identifier: BSD-3-Clause-Clear */
/* /*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef ATH11K_HW_H #ifndef ATH11K_HW_H
...@@ -189,11 +190,11 @@ struct ath11k_hw_params { ...@@ -189,11 +190,11 @@ struct ath11k_hw_params {
const struct ath11k_hw_hal_params *hal_params; const struct ath11k_hw_hal_params *hal_params;
bool supports_dynamic_smps_6ghz; bool supports_dynamic_smps_6ghz;
bool alloc_cacheable_memory; bool alloc_cacheable_memory;
bool wakeup_mhi;
bool supports_rssi_stats; bool supports_rssi_stats;
bool fw_wmi_diag_event; bool fw_wmi_diag_event;
bool current_cc_support; bool current_cc_support;
bool dbr_debug_support; bool dbr_debug_support;
bool global_reset;
}; };
struct ath11k_hw_ops { struct ath11k_hw_ops {
...@@ -290,10 +291,16 @@ enum ath11k_bd_ie_board_type { ...@@ -290,10 +291,16 @@ enum ath11k_bd_ie_board_type {
ATH11K_BD_IE_BOARD_DATA = 1, ATH11K_BD_IE_BOARD_DATA = 1,
}; };
enum ath11k_bd_ie_regdb_type {
ATH11K_BD_IE_REGDB_NAME = 0,
ATH11K_BD_IE_REGDB_DATA = 1,
};
enum ath11k_bd_ie_type { enum ath11k_bd_ie_type {
/* contains sub IEs of enum ath11k_bd_ie_board_type */ /* contains sub IEs of enum ath11k_bd_ie_board_type */
ATH11K_BD_IE_BOARD = 0, ATH11K_BD_IE_BOARD = 0,
ATH11K_BD_IE_BOARD_EXT = 1, /* contains sub IEs of enum ath11k_bd_ie_regdb_type */
ATH11K_BD_IE_REGDB = 1,
}; };
struct ath11k_hw_regs { struct ath11k_hw_regs {
...@@ -361,4 +368,16 @@ extern const struct ath11k_hw_regs qca6390_regs; ...@@ -361,4 +368,16 @@ extern const struct ath11k_hw_regs qca6390_regs;
extern const struct ath11k_hw_regs qcn9074_regs; extern const struct ath11k_hw_regs qcn9074_regs;
extern const struct ath11k_hw_regs wcn6855_regs; extern const struct ath11k_hw_regs wcn6855_regs;
static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
{
switch (type) {
case ATH11K_BD_IE_BOARD:
return "board data";
case ATH11K_BD_IE_REGDB:
return "regdb data";
}
return "unknown";
}
#endif #endif
This diff is collapsed.
...@@ -130,7 +130,7 @@ extern const struct htt_rx_ring_tlv_filter ath11k_mac_mon_status_filter_default; ...@@ -130,7 +130,7 @@ extern const struct htt_rx_ring_tlv_filter ath11k_mac_mon_status_filter_default;
#define ATH11K_SCAN_11D_INTERVAL 600000 #define ATH11K_SCAN_11D_INTERVAL 600000
#define ATH11K_11D_INVALID_VDEV_ID 0xFFFF #define ATH11K_11D_INVALID_VDEV_ID 0xFFFF
void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id, bool wait); void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id);
void ath11k_mac_11d_scan_stop(struct ath11k *ar); void ath11k_mac_11d_scan_stop(struct ath11k *ar);
void ath11k_mac_11d_scan_stop_all(struct ath11k_base *ab); void ath11k_mac_11d_scan_stop_all(struct ath11k_base *ab);
...@@ -172,4 +172,5 @@ enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher); ...@@ -172,4 +172,5 @@ enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher);
void ath11k_mac_handle_beacon(struct ath11k *ar, struct sk_buff *skb); void ath11k_mac_handle_beacon(struct ath11k *ar, struct sk_buff *skb);
void ath11k_mac_handle_beacon_miss(struct ath11k *ar, u32 vdev_id); void ath11k_mac_handle_beacon_miss(struct ath11k *ar, u32 vdev_id);
void ath11k_mac_bcn_tx_event(struct ath11k_vif *arvif); void ath11k_mac_bcn_tx_event(struct ath11k_vif *arvif);
int ath11k_mac_wait_tx_complete(struct ath11k *ar);
#endif #endif
This diff is collapsed.
...@@ -16,19 +16,6 @@ ...@@ -16,19 +16,6 @@
#define MHICTRL 0x38 #define MHICTRL 0x38
#define MHICTRL_RESET_MASK 0x2 #define MHICTRL_RESET_MASK 0x2
enum ath11k_mhi_state {
ATH11K_MHI_INIT,
ATH11K_MHI_DEINIT,
ATH11K_MHI_POWER_ON,
ATH11K_MHI_POWER_OFF,
ATH11K_MHI_FORCE_POWER_OFF,
ATH11K_MHI_SUSPEND,
ATH11K_MHI_RESUME,
ATH11K_MHI_TRIGGER_RDDM,
ATH11K_MHI_RDDM,
ATH11K_MHI_RDDM_DONE,
};
int ath11k_mhi_start(struct ath11k_pci *ar_pci); int ath11k_mhi_start(struct ath11k_pci *ar_pci);
void ath11k_mhi_stop(struct ath11k_pci *ar_pci); void ath11k_mhi_stop(struct ath11k_pci *ar_pci);
int ath11k_mhi_register(struct ath11k_pci *ar_pci); int ath11k_mhi_register(struct ath11k_pci *ar_pci);
...@@ -36,7 +23,7 @@ void ath11k_mhi_unregister(struct ath11k_pci *ar_pci); ...@@ -36,7 +23,7 @@ void ath11k_mhi_unregister(struct ath11k_pci *ar_pci);
void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab); void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab);
void ath11k_mhi_clear_vector(struct ath11k_base *ab); void ath11k_mhi_clear_vector(struct ath11k_base *ab);
void ath11k_mhi_suspend(struct ath11k_pci *ar_pci); int ath11k_mhi_suspend(struct ath11k_pci *ar_pci);
void ath11k_mhi_resume(struct ath11k_pci *ar_pci); int ath11k_mhi_resume(struct ath11k_pci *ar_pci);
#endif #endif
This diff is collapsed.
/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* SPDX-License-Identifier: BSD-3-Clause-Clear */
/* /*
* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef _ATH11K_PCI_H #ifndef _ATH11K_PCI_H
#define _ATH11K_PCI_H #define _ATH11K_PCI_H
...@@ -52,23 +53,8 @@ ...@@ -52,23 +53,8 @@
#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
struct ath11k_msi_user {
char *name;
int num_vectors;
u32 base_vector;
};
struct ath11k_msi_config {
int total_vectors;
int total_users;
struct ath11k_msi_user *users;
};
enum ath11k_pci_flags { enum ath11k_pci_flags {
ATH11K_PCI_FLAG_INIT_DONE,
ATH11K_PCI_FLAG_IS_MSI_64,
ATH11K_PCI_ASPM_RESTORE, ATH11K_PCI_ASPM_RESTORE,
ATH11K_PCI_FLAG_MULTI_MSI_VECTORS,
}; };
struct ath11k_pci { struct ath11k_pci {
...@@ -76,10 +62,8 @@ struct ath11k_pci { ...@@ -76,10 +62,8 @@ struct ath11k_pci {
struct ath11k_base *ab; struct ath11k_base *ab;
u16 dev_id; u16 dev_id;
char amss_path[100]; char amss_path[100];
u32 msi_ep_base_data;
struct mhi_controller *mhi_ctrl; struct mhi_controller *mhi_ctrl;
const struct ath11k_msi_config *msi_config; const struct ath11k_msi_config *msi_config;
unsigned long mhi_state;
u32 register_window; u32 register_window;
/* protects register_window above */ /* protects register_window above */
...@@ -88,8 +72,6 @@ struct ath11k_pci { ...@@ -88,8 +72,6 @@ struct ath11k_pci {
/* enum ath11k_pci_flags */ /* enum ath11k_pci_flags */
unsigned long flags; unsigned long flags;
u16 link_ctl; u16 link_ctl;
unsigned long irq_flags;
}; };
static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
...@@ -97,11 +79,5 @@ static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) ...@@ -97,11 +79,5 @@ static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
return (struct ath11k_pci *)ab->drv_priv; return (struct ath11k_pci *)ab->drv_priv;
} }
int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name, int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector);
int *num_vectors, u32 *user_base_data,
u32 *base_vector);
int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector);
void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value);
u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset);
#endif #endif
This diff is collapsed.
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _ATH11K_PCI_CMN_H
#define _ATH11K_PCI_CMN_H
#include "core.h"
#define ATH11K_PCI_IRQ_CE0_OFFSET 3
#define ATH11K_PCI_IRQ_DP_OFFSET 14
#define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000
#define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c
#define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
#define ATH11K_PCI_WINDOW_START 0x80000
#define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
/* BAR0 + 4k is always accessible, and no
* need to force wakeup.
* 4K - 32 = 0xFE0
*/
#define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0
int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
int *num_vectors, u32 *user_base_data,
u32 *base_vector);
void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value);
u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset);
void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
u32 *msi_addr_hi);
void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx);
void ath11k_pcic_free_irq(struct ath11k_base *ab);
int ath11k_pcic_config_irq(struct ath11k_base *ab);
void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab);
void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab);
void ath11k_pcic_stop(struct ath11k_base *ab);
int ath11k_pcic_start(struct ath11k_base *ab);
int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
u8 *ul_pipe, u8 *dl_pipe);
void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab);
void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab);
int ath11k_pcic_init_msi_config(struct ath11k_base *ab);
#endif
This diff is collapsed.
/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* SPDX-License-Identifier: BSD-3-Clause-Clear */
/* /*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#ifndef ATH11K_PEER_H #ifndef ATH11K_PEER_H
...@@ -20,6 +21,11 @@ struct ath11k_peer { ...@@ -20,6 +21,11 @@ struct ath11k_peer {
struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
struct dp_rx_tid rx_tid[IEEE80211_NUM_TIDS + 1]; struct dp_rx_tid rx_tid[IEEE80211_NUM_TIDS + 1];
/* peer id based rhashtable list pointer */
struct rhash_head rhash_id;
/* peer addr based rhashtable list pointer */
struct rhash_head rhash_addr;
/* Info used in MMIC verification of /* Info used in MMIC verification of
* RX fragments * RX fragments
*/ */
...@@ -47,5 +53,7 @@ int ath11k_wait_for_peer_delete_done(struct ath11k *ar, u32 vdev_id, ...@@ -47,5 +53,7 @@ int ath11k_wait_for_peer_delete_done(struct ath11k *ar, u32 vdev_id,
const u8 *addr); const u8 *addr);
struct ath11k_peer *ath11k_peer_find_by_vdev_id(struct ath11k_base *ab, struct ath11k_peer *ath11k_peer_find_by_vdev_id(struct ath11k_base *ab,
int vdev_id); int vdev_id);
int ath11k_peer_rhash_tbl_init(struct ath11k_base *ab);
void ath11k_peer_rhash_tbl_destroy(struct ath11k_base *ab);
int ath11k_peer_rhash_delete(struct ath11k_base *ab, struct ath11k_peer *peer);
#endif /* _PEER_H_ */ #endif /* _PEER_H_ */
This diff is collapsed.
This diff is collapsed.
...@@ -32,5 +32,5 @@ struct ieee80211_regdomain * ...@@ -32,5 +32,5 @@ struct ieee80211_regdomain *
ath11k_reg_build_regd(struct ath11k_base *ab, ath11k_reg_build_regd(struct ath11k_base *ab,
struct cur_regulatory_info *reg_info, bool intersect); struct cur_regulatory_info *reg_info, bool intersect);
int ath11k_regd_update(struct ath11k *ar); int ath11k_regd_update(struct ath11k *ar);
int ath11k_reg_update_chan_list(struct ath11k *ar); int ath11k_reg_update_chan_list(struct ath11k *ar, bool wait);
#endif #endif
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...@@ -1538,7 +1538,7 @@ static int ath6kl_htc_rx_alloc(struct htc_target *target, ...@@ -1538,7 +1538,7 @@ static int ath6kl_htc_rx_alloc(struct htc_target *target,
queue, n_msg); queue, n_msg);
/* /*
* This is due to unavailabilty of buffers to rx entire data. * This is due to unavailability of buffers to rx entire data.
* Return no error so that free buffers from queue can be used * Return no error so that free buffers from queue can be used
* to receive partial data. * to receive partial data.
*/ */
......
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...@@ -177,7 +177,7 @@ static void ar9003_hw_iqcal_collect(struct ath_hw *ah) ...@@ -177,7 +177,7 @@ static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
int i; int i;
/* Accumulate IQ cal measures for active chains */ /* Accumulate IQ cal measures for active chains */
for (i = 0; i < AR5416_MAX_CHAINS; i++) { for (i = 0; i < AR9300_MAX_CHAINS; i++) {
if (ah->txchainmask & BIT(i)) { if (ah->txchainmask & BIT(i)) {
ah->totalPowerMeasI[i] += ah->totalPowerMeasI[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
......
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