Commit eddb0473 authored by Ben Skeggs's avatar Ben Skeggs

drm/nouveau/sec2/gp102: allow module to load when LSFW is missing

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent b9c246ad
...@@ -28,6 +28,14 @@ ...@@ -28,6 +28,14 @@
#include <nvfw/flcn.h> #include <nvfw/flcn.h>
#include <nvfw/sec2.h> #include <nvfw/sec2.h>
int
gp102_sec2_nofw(struct nvkm_sec2 *sec2, int ver,
const struct nvkm_sec2_fwif *fwif)
{
nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n");
return 0;
}
static int static int
gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr) gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr)
{ {
...@@ -328,8 +336,9 @@ MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin"); ...@@ -328,8 +336,9 @@ MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin");
static const struct nvkm_sec2_fwif static const struct nvkm_sec2_fwif
gp102_sec2_fwif[] = { gp102_sec2_fwif[] = {
{ 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 }, { 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 },
{ 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 }, { 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 },
{ -1, gp102_sec2_nofw, &gp102_sec2 },
{} {}
}; };
......
...@@ -20,6 +20,7 @@ struct nvkm_sec2_fwif { ...@@ -20,6 +20,7 @@ struct nvkm_sec2_fwif {
const struct nvkm_acr_lsf_func *acr; const struct nvkm_acr_lsf_func *acr;
}; };
int gp102_sec2_nofw(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *);
int gp102_sec2_load(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *); int gp102_sec2_load(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *);
extern const struct nvkm_sec2_func gp102_sec2; extern const struct nvkm_sec2_func gp102_sec2;
extern const struct nvkm_acr_lsf_func gp102_sec2_acr_1; extern const struct nvkm_acr_lsf_func gp102_sec2_acr_1;
......
...@@ -49,13 +49,6 @@ tu102_sec2 = { ...@@ -49,13 +49,6 @@ tu102_sec2 = {
.initmsg = gp102_sec2_initmsg, .initmsg = gp102_sec2_initmsg,
}; };
static int
tu102_sec2_nofw(struct nvkm_sec2 *sec2, int ver,
const struct nvkm_sec2_fwif *fwif)
{
return 0;
}
MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin"); MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin"); MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin");
MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin"); MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin");
...@@ -75,7 +68,7 @@ MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin"); ...@@ -75,7 +68,7 @@ MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin");
static const struct nvkm_sec2_fwif static const struct nvkm_sec2_fwif
tu102_sec2_fwif[] = { tu102_sec2_fwif[] = {
{ 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 }, { 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
{ -1, tu102_sec2_nofw, &tu102_sec2 } { -1, gp102_sec2_nofw, &tu102_sec2 }
}; };
int int
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment