Commit ee4e92c2 authored by Harini Katakam's avatar Harini Katakam Committed by Jakub Kicinski

net: macb: Enable PTP unicast

Enable transmission and reception of PTP unicast packets by
updating PTP unicast config bit and setting current HW mac
address as allowed address in PTP unicast filter registers.
Signed-off-by: default avatarHarini Katakam <harini.katakam@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Signed-off-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent adee474a
...@@ -95,6 +95,8 @@ ...@@ -95,6 +95,8 @@
#define GEM_SA4B 0x00A0 /* Specific4 Bottom */ #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
#define GEM_SA4T 0x00A4 /* Specific4 Top */ #define GEM_SA4T 0x00A4 /* Specific4 Top */
#define GEM_WOL 0x00b8 /* Wake on LAN */ #define GEM_WOL 0x00b8 /* Wake on LAN */
#define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
#define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
#define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */ #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
#define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */ #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
#define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */ #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
...@@ -245,6 +247,8 @@ ...@@ -245,6 +247,8 @@
#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
#define MACB_TZQ_SIZE 1 #define MACB_TZQ_SIZE 1
#define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */ #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */
#define MACB_PTPUNI_OFFSET 20 /* PTP Unicast packet enable */
#define MACB_PTPUNI_SIZE 1
#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
#define MACB_OSSMODE_SIZE 1 #define MACB_OSSMODE_SIZE 1
#define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */ #define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */
......
...@@ -287,6 +287,11 @@ static void macb_set_hwaddr(struct macb *bp) ...@@ -287,6 +287,11 @@ static void macb_set_hwaddr(struct macb *bp)
top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
macb_or_gem_writel(bp, SA1T, top); macb_or_gem_writel(bp, SA1T, top);
if (gem_has_ptp(bp)) {
gem_writel(bp, RXPTPUNI, bottom);
gem_writel(bp, TXPTPUNI, bottom);
}
/* Clear unused address register sets */ /* Clear unused address register sets */
macb_or_gem_writel(bp, SA2B, 0); macb_or_gem_writel(bp, SA2B, 0);
macb_or_gem_writel(bp, SA2T, 0); macb_or_gem_writel(bp, SA2T, 0);
...@@ -773,8 +778,12 @@ static void macb_mac_link_up(struct phylink_config *config, ...@@ -773,8 +778,12 @@ static void macb_mac_link_up(struct phylink_config *config,
spin_unlock_irqrestore(&bp->lock, flags); spin_unlock_irqrestore(&bp->lock, flags);
/* Enable Rx and Tx */ /* Enable Rx and Tx; Enable PTP unicast */
macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE)); ctrl = macb_readl(bp, NCR);
if (gem_has_ptp(bp))
ctrl |= MACB_BIT(PTPUNI);
macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));
netif_tx_wake_all_queues(ndev); netif_tx_wake_all_queues(ndev);
} }
......
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