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Commit eeadcd2a authored by Chia-Yuan Li's avatar Chia-Yuan Li Committed by Kalle Valo
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rtw89: ser: configure D-MAC interrupt mask 

These interrupts are used by firmware to recover hardware. Create
functions to set specific D-MAC masks to replace plain register settings.
Signed-off-by: default avatarChia-Yuan Li <leo.li@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220408001353.17188-3-pkshih@realtek.com
parent 5ddfffd6
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Showing with 1091 additions and 19 deletions
drivers/net/wireless/realtek/rtw89/core.h
View file @ eeadcd2a
...@@ -2293,6 +2293,34 @@ struct rtw89_page_regs { ...@@ -2293,6 +2293,34 @@ struct rtw89_page_regs {
u32 wp_page_info1; u32 wp_page_info1;
}; };
struct rtw89_imr_info {
u32 wdrls_imr_set;
u32 wsec_imr_reg;
u32 wsec_imr_set;
u32 mpdu_tx_imr_set;
u32 mpdu_rx_imr_set;
u32 sta_sch_imr_set;
u32 txpktctl_imr_b0_reg;
u32 txpktctl_imr_b0_clr;
u32 txpktctl_imr_b0_set;
u32 txpktctl_imr_b1_reg;
u32 txpktctl_imr_b1_clr;
u32 txpktctl_imr_b1_set;
u32 wde_imr_clr;
u32 wde_imr_set;
u32 ple_imr_clr;
u32 ple_imr_set;
u32 host_disp_imr_clr;
u32 host_disp_imr_set;
u32 cpu_disp_imr_clr;
u32 cpu_disp_imr_set;
u32 other_disp_imr_clr;
u32 other_disp_imr_set;
u32 bbrpt_chinfo_err_imr_reg;
u32 bbrpt_err_imr_set;
u32 bbrpt_dfs_err_imr_reg;
};
struct rtw89_chip_info { struct rtw89_chip_info {
enum rtw89_core_chip_id chip_id; enum rtw89_core_chip_id chip_id;
const struct rtw89_chip_ops *ops; const struct rtw89_chip_ops *ops;
...@@ -2378,6 +2406,7 @@ struct rtw89_chip_info { ...@@ -2378,6 +2406,7 @@ struct rtw89_chip_info {
const struct rtw89_page_regs *page_regs; const struct rtw89_page_regs *page_regs;
const struct rtw89_reg_def *dcfo_comp; const struct rtw89_reg_def *dcfo_comp;
u8 dcfo_comp_sft; u8 dcfo_comp_sft;
const struct rtw89_imr_info *imr_info;
}; };
union rtw89_bus_info { union rtw89_bus_info {
......
drivers/net/wireless/realtek/rtw89/mac.c
View file @ eeadcd2a
...@@ -2607,6 +2607,136 @@ static int band1_enable(struct rtw89_dev *rtwdev) ...@@ -2607,6 +2607,136 @@ static int band1_enable(struct rtw89_dev *rtwdev)
return 0; return 0;
} }
static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR);
rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
}
static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
}
static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
B_AX_TX_GET_ERRPKTID_INT_EN |
B_AX_TX_NXT_ERRPKTID_INT_EN |
B_AX_TX_MPDU_SIZE_ZERO_INT_EN |
B_AX_TX_OFFSET_ERR_INT_EN |
B_AX_TX_HDR3_SIZE_ERR_INT_EN);
if (chip_id == RTL8852C)
rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
B_AX_TX_ETH_TYPE_ERR_EN |
B_AX_TX_LLC_PRE_ERR_EN |
B_AX_TX_NW_TYPE_ERR_EN |
B_AX_TX_KSRCH_ERR_EN);
rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,
imr->mpdu_tx_imr_set);
rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR,
B_AX_GETPKTID_ERR_INT_EN |
B_AX_MHDRLEN_ERR_INT_EN |
B_AX_RPT_ERR_INT_EN);
rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,
imr->mpdu_rx_imr_set);
}
static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
B_AX_SEARCH_HANG_TIMEOUT_INT_EN |
B_AX_RPT_HANG_TIMEOUT_INT_EN |
B_AX_PLE_B_PKTID_ERR_INT_EN);
rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
imr->sta_sch_imr_set);
}
static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
imr->txpktctl_imr_b0_clr);
rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
imr->txpktctl_imr_b0_set);
rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
imr->txpktctl_imr_b1_clr);
rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
imr->txpktctl_imr_b1_set);
}
static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
}
static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
}
static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev)
{
rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,
B_AX_PKTIN_GETPKTID_ERR_INT_EN);
}
static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
imr->host_disp_imr_clr);
rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
imr->host_disp_imr_set);
rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
imr->cpu_disp_imr_clr);
rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
imr->cpu_disp_imr_set);
rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
imr->other_disp_imr_clr);
rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
imr->other_disp_imr_set);
}
static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev)
{
rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR);
rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);
}
static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)
{
const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
rtw89_write32_set(rtwdev, R_AX_BBRPT_COM_ERR_IMR,
B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN);
rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
B_AX_BBRPT_CHINFO_IMR_CLR);
rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
imr->bbrpt_err_imr_set);
rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
B_AX_BBRPT_DFS_TO_ERR_INT_EN);
rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);
}
static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,
enum rtw89_mac_hwmod_sel sel) enum rtw89_mac_hwmod_sel sel)
{ {
...@@ -2621,25 +2751,17 @@ static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, ...@@ -2621,25 +2751,17 @@ static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,
} }
if (sel == RTW89_DMAC_SEL) { if (sel == RTW89_DMAC_SEL) {
rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, rtw89_wdrls_imr_enable(rtwdev);
B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | rtw89_wsec_imr_enable(rtwdev);
B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | rtw89_mpdu_trx_imr_enable(rtwdev);
B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN); rtw89_sta_sch_imr_enable(rtwdev);
rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1, rtw89_txpktctl_imr_enable(rtwdev);
B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | rtw89_wde_imr_enable(rtwdev);
B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN); rtw89_ple_imr_enable(rtwdev);
rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, rtw89_pktin_imr_enable(rtwdev);
B_AX_HDT_PKT_FAIL_DBG_INT_EN | rtw89_dispatcher_imr_enable(rtwdev);
B_AX_HDT_OFFSET_UNMATCH_INT_EN); rtw89_cpuio_imr_enable(rtwdev);
rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, rtw89_bbrpt_imr_enable(rtwdev);
B_AX_CPU_SHIFT_EN_ERR_INT_EN);
rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR,
B_AX_PLE_GETNPG_STRPG_ERR_INT_EN);
rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR,
B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN);
rtw89_write32_set(rtwdev, R_AX_HD0IMR, B_AX_WDT_PTFM_INT_EN);
rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR,
B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN);
} else if (sel == RTW89_CMAC_SEL) { } else if (sel == RTW89_CMAC_SEL) {
reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx);
rtw89_write32_clr(rtwdev, reg, rtw89_write32_clr(rtwdev, reg,
......
drivers/net/wireless/realtek/rtw89/reg.h
View file @ eeadcd2a
This diff is collapsed.
drivers/net/wireless/realtek/rtw89/rtw8852a.c
View file @ eeadcd2a
...@@ -408,6 +408,34 @@ static const struct rtw89_reg_def rtw8852a_dcfo_comp = { ...@@ -408,6 +408,34 @@ static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
}; };
static const struct rtw89_imr_info rtw8852a_imr_info = {
.wdrls_imr_set = B_AX_WDRLS_IMR_SET,
.wsec_imr_reg = R_AX_SEC_DEBUG,
.wsec_imr_set = B_AX_IMR_ERROR,
.mpdu_tx_imr_set = 0,
.mpdu_rx_imr_set = 0,
.sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
.txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
.txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
.txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
.txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
.txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
.txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
.wde_imr_clr = B_AX_WDE_IMR_CLR,
.wde_imr_set = B_AX_WDE_IMR_SET,
.ple_imr_clr = B_AX_PLE_IMR_CLR,
.ple_imr_set = B_AX_PLE_IMR_SET,
.host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
.host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
.cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
.cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
.other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
.other_disp_imr_set = 0,
.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
.bbrpt_err_imr_set = 0,
.bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
};
static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
struct rtw8852a_efuse *map) struct rtw8852a_efuse *map)
{ {
...@@ -2112,6 +2140,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = { ...@@ -2112,6 +2140,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.page_regs = &rtw8852a_page_regs, .page_regs = &rtw8852a_page_regs,
.dcfo_comp = &rtw8852a_dcfo_comp, .dcfo_comp = &rtw8852a_dcfo_comp,
.dcfo_comp_sft = 3, .dcfo_comp_sft = 3,
.imr_info = &rtw8852a_imr_info
}; };
EXPORT_SYMBOL(rtw8852a_chip_info); EXPORT_SYMBOL(rtw8852a_chip_info);
......
drivers/net/wireless/realtek/rtw89/rtw8852c.c
View file @ eeadcd2a
...@@ -51,6 +51,34 @@ static const struct rtw89_reg_def rtw8852c_dcfo_comp = { ...@@ -51,6 +51,34 @@ static const struct rtw89_reg_def rtw8852c_dcfo_comp = {
R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK
}; };
static const struct rtw89_imr_info rtw8852c_imr_info = {
.wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1,
.wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR,
.wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR,
.mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1,
.mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1,
.sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
.txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR,
.txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1,
.txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1,
.txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR,
.txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1,
.txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1,
.wde_imr_clr = B_AX_WDE_IMR_CLR_V1,
.wde_imr_set = B_AX_WDE_IMR_SET_V1,
.ple_imr_clr = B_AX_PLE_IMR_CLR_V1,
.ple_imr_set = B_AX_PLE_IMR_SET_V1,
.host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1,
.host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1,
.cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1,
.cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1,
.other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1,
.other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1,
.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR,
.bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1,
.bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR,
};
static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
{ {
u32 val32; u32 val32;
...@@ -572,6 +600,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = { ...@@ -572,6 +600,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.page_regs = &rtw8852c_page_regs, .page_regs = &rtw8852c_page_regs,
.dcfo_comp = &rtw8852c_dcfo_comp, .dcfo_comp = &rtw8852c_dcfo_comp,
.dcfo_comp_sft = 5, .dcfo_comp_sft = 5,
.imr_info = &rtw8852c_imr_info
}; };
EXPORT_SYMBOL(rtw8852c_chip_info); EXPORT_SYMBOL(rtw8852c_chip_info);
......
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