Commit ef5bf0b5 authored by Linus Torvalds's avatar Linus Torvalds

Merge master.kernel.org:/home/davem/BK/sparc-2.5

into home.transmeta.com:/home/torvalds/v2.5/linux
parents 055be65c 160c1da3
...@@ -99,6 +99,7 @@ ...@@ -99,6 +99,7 @@
#include <linux/usbdevice_fs.h> #include <linux/usbdevice_fs.h>
#include <linux/nbd.h> #include <linux/nbd.h>
#include <linux/random.h> #include <linux/random.h>
#include <linux/filter.h>
/* Use this to get at 32-bit user passed pointers. /* Use this to get at 32-bit user passed pointers.
See sys_sparc32.c for description about these. */ See sys_sparc32.c for description about these. */
...@@ -1668,6 +1669,40 @@ static int sg_ioctl_trans(unsigned int fd, unsigned int cmd, unsigned long arg) ...@@ -1668,6 +1669,40 @@ static int sg_ioctl_trans(unsigned int fd, unsigned int cmd, unsigned long arg)
return err; return err;
} }
struct sock_fprog32 {
__u16 len;
__u32 filter;
};
#define PPPIOCSPASS32 _IOW('t', 71, struct sock_fprog32)
#define PPPIOCSACTIVE32 _IOW('t', 70, struct sock_fprog32)
static int ppp_sock_fprog_ioctl_trans(unsigned int fd, unsigned int cmd, unsigned long arg)
{
struct sock_fprog32 *u_fprog32 = (struct sock_fprog32 *) arg;
struct sock_fprog *u_fprog64 = alloc_user_space(sizeof(struct sock_fprog));
void *fptr64;
u32 fptr32;
u16 flen;
if (get_user(flen, &u_fprog32->len) ||
get_user(fptr32, &u_fprog32->filter))
return -EFAULT;
fptr64 = (void *) A(fptr32);
if (put_user(flen, &u_fprog64->len) ||
put_user(fptr64, &u_fprog64->filter))
return -EFAULT;
if (cmd == PPPIOCSPASS32)
cmd = PPPIOCSPASS;
else
cmd = PPPIOCSACTIVE;
return sys_ioctl(fd, cmd, (unsigned long) u_fprog64);
}
struct ppp_option_data32 { struct ppp_option_data32 {
__kernel_caddr_t32 ptr; __kernel_caddr_t32 ptr;
__u32 length; __u32 length;
...@@ -4237,13 +4272,16 @@ COMPATIBLE_IOCTL(PPPIOCGMRU) ...@@ -4237,13 +4272,16 @@ COMPATIBLE_IOCTL(PPPIOCGMRU)
COMPATIBLE_IOCTL(PPPIOCSMRU) COMPATIBLE_IOCTL(PPPIOCSMRU)
COMPATIBLE_IOCTL(PPPIOCSMAXCID) COMPATIBLE_IOCTL(PPPIOCSMAXCID)
COMPATIBLE_IOCTL(PPPIOCGXASYNCMAP) COMPATIBLE_IOCTL(PPPIOCGXASYNCMAP)
COMPATIBLE_IOCTL(LPGETSTATUS)
COMPATIBLE_IOCTL(PPPIOCSXASYNCMAP) COMPATIBLE_IOCTL(PPPIOCSXASYNCMAP)
COMPATIBLE_IOCTL(PPPIOCXFERUNIT) COMPATIBLE_IOCTL(PPPIOCXFERUNIT)
/* PPPIOCSCOMPRESS is translated */
COMPATIBLE_IOCTL(PPPIOCGNPMODE) COMPATIBLE_IOCTL(PPPIOCGNPMODE)
COMPATIBLE_IOCTL(PPPIOCSNPMODE) COMPATIBLE_IOCTL(PPPIOCSNPMODE)
/* PPPIOCSPASS is translated */
/* PPPIOCSACTIVE is translated */
COMPATIBLE_IOCTL(PPPIOCGDEBUG) COMPATIBLE_IOCTL(PPPIOCGDEBUG)
COMPATIBLE_IOCTL(PPPIOCSDEBUG) COMPATIBLE_IOCTL(PPPIOCSDEBUG)
/* PPPIOCGIDLE is translated */
COMPATIBLE_IOCTL(PPPIOCNEWUNIT) COMPATIBLE_IOCTL(PPPIOCNEWUNIT)
COMPATIBLE_IOCTL(PPPIOCATTACH) COMPATIBLE_IOCTL(PPPIOCATTACH)
COMPATIBLE_IOCTL(PPPIOCDETACH) COMPATIBLE_IOCTL(PPPIOCDETACH)
...@@ -4252,6 +4290,8 @@ COMPATIBLE_IOCTL(PPPIOCCONNECT) ...@@ -4252,6 +4290,8 @@ COMPATIBLE_IOCTL(PPPIOCCONNECT)
COMPATIBLE_IOCTL(PPPIOCDISCONN) COMPATIBLE_IOCTL(PPPIOCDISCONN)
COMPATIBLE_IOCTL(PPPIOCATTCHAN) COMPATIBLE_IOCTL(PPPIOCATTCHAN)
COMPATIBLE_IOCTL(PPPIOCGCHAN) COMPATIBLE_IOCTL(PPPIOCGCHAN)
/* LP */
COMPATIBLE_IOCTL(LPGETSTATUS)
/* PPPOX */ /* PPPOX */
COMPATIBLE_IOCTL(PPPOEIOCSFWD) COMPATIBLE_IOCTL(PPPOEIOCSFWD)
COMPATIBLE_IOCTL(PPPOEIOCDFWD) COMPATIBLE_IOCTL(PPPOEIOCDFWD)
...@@ -4677,6 +4717,8 @@ HANDLE_IOCTL(FDWERRORGET32, fd_ioctl_trans) ...@@ -4677,6 +4717,8 @@ HANDLE_IOCTL(FDWERRORGET32, fd_ioctl_trans)
HANDLE_IOCTL(SG_IO,sg_ioctl_trans) HANDLE_IOCTL(SG_IO,sg_ioctl_trans)
HANDLE_IOCTL(PPPIOCGIDLE32, ppp_ioctl_trans) HANDLE_IOCTL(PPPIOCGIDLE32, ppp_ioctl_trans)
HANDLE_IOCTL(PPPIOCSCOMPRESS32, ppp_ioctl_trans) HANDLE_IOCTL(PPPIOCSCOMPRESS32, ppp_ioctl_trans)
HANDLE_IOCTL(PPPIOCSPASS32, ppp_sock_fprog_ioctl_trans)
HANDLE_IOCTL(PPPIOCSACTIVE32, ppp_sock_fprog_ioctl_trans)
HANDLE_IOCTL(MTIOCGET32, mt_ioctl_trans) HANDLE_IOCTL(MTIOCGET32, mt_ioctl_trans)
HANDLE_IOCTL(MTIOCPOS32, mt_ioctl_trans) HANDLE_IOCTL(MTIOCPOS32, mt_ioctl_trans)
HANDLE_IOCTL(MTIOCGETCONFIG32, mt_ioctl_trans) HANDLE_IOCTL(MTIOCGETCONFIG32, mt_ioctl_trans)
......
...@@ -212,6 +212,8 @@ csum_partial: ...@@ -212,6 +212,8 @@ csum_partial:
mov 1, %g5 /* IEU0 Group */ mov 1, %g5 /* IEU0 Group */
cmp %o1, 6 /* IEU1 */ cmp %o1, 6 /* IEU1 */
bl,pn %icc, 21f /* CTI */ bl,pn %icc, 21f /* CTI */
andcc %o0, 1, %g0 /* IEU1 Group */
bne,pn %icc, csump_really_slow /* CTI */
andcc %o0, 2, %g0 /* IEU1 Group */ andcc %o0, 2, %g0 /* IEU1 Group */
be,pt %icc, 1f /* CTI */ be,pt %icc, 1f /* CTI */
and %o0, 4, %g7 /* IEU0 */ and %o0, 4, %g7 /* IEU0 */
...@@ -449,3 +451,96 @@ csum_partial: ...@@ -449,3 +451,96 @@ csum_partial:
add %o2, 1, %o2 /* IEU0 */ add %o2, 1, %o2 /* IEU0 */
1: ba,pt %xcc, 25b /* CTI Group */ 1: ba,pt %xcc, 25b /* CTI Group */
sllx %o2, 32, %g1 /* IEU0 */ sllx %o2, 32, %g1 /* IEU0 */
/* When buff is byte aligned and len is large, we backoff to
* this really slow handling. The issue is that we cannot do
* the VIS stuff when buff is byte aligned as unaligned.c will
* not fix it up.
*/
csump_really_slow:
mov %o0, %o3
mov %o1, %o4
cmp %o1, 0
ble,pn %icc, 9f
mov 0, %o0
andcc %o3, 1, %o5
be,pt %icc, 1f
sra %o4, 1, %g3
add %o1, -1, %o4
ldub [%o3], %o0
add %o3, 1, %o3
sra %o4, 1, %g3
1:
cmp %g3, 0
be,pt %icc, 3f
and %o4, 1, %g2
and %o3, 2, %g2
brz,a,pt %g2, 1f
sra %g3, 1, %g3
add %g3, -1, %g3
add %o4, -2, %o4
lduh [%o3], %g2
add %o3, 2, %o3
add %o0, %g2, %o0
sra %g3, 1, %g3
1:
cmp %g3, 0
be,pt %icc, 2f
and %o4, 2, %g2
1:
ld [%o3], %g2
addcc %o0, %g2, %o0
addx %o0, %g0, %o0
addcc %g3, -1, %g3
bne,pt %icc, 1b
add %o3, 4, %o3
srl %o0, 16, %o1
sethi %hi(64512), %g2
or %g2, 1023, %g2
and %o0, %g2, %g3
add %g3, %o1, %g3
srl %g3, 16, %o0
and %g3, %g2, %g2
add %g2, %o0, %g3
sll %g3, 16, %g3
srl %g3, 16, %o0
and %o4, 2, %g2
2:
cmp %g2, 0
be,pt %icc, 3f
and %o4, 1, %g2
lduh [%o3], %g2
add %o3, 2, %o3
add %o0, %g2, %o0
and %o4, 1, %g2
3:
cmp %g2, 0
be,pt %icc, 1f
srl %o0, 16, %o1
ldub [%o3], %g2
sll %g2, 8, %g2
add %o0, %g2, %o0
srl %o0, 16, %o1
1:
sethi %hi(64512), %g2
or %g2, 1023, %g2
cmp %o5, 0
and %o0, %g2, %g3
add %g3, %o1, %g3
srl %g3, 16, %o0
and %g3, %g2, %g2
add %g2, %o0, %g3
sll %g3, 16, %g3
srl %g3, 16, %o0
srl %g3, 24, %g3
and %o0, 255, %g2
sll %g2, 8, %g2
bne,pt %icc, 1f
or %g3, %g2, %g2
9:
mov %o0, %g2
1:
addcc %g2, %o2, %g2
addx %g2, %g0, %g2
retl
srl %g2, 0, %o0
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment