Commit f027f491 authored by Ben Skeggs's avatar Ben Skeggs

drm/nouveau/gpuobj: separate allocation from nvkm_object

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 227c95d9
......@@ -7,30 +7,33 @@ struct nvkm_vma;
struct nvkm_vm;
#define NVOBJ_FLAG_ZERO_ALLOC 0x00000001
#define NVOBJ_FLAG_ZERO_FREE 0x00000002
#define NVOBJ_FLAG_HEAP 0x00000004
struct nvkm_gpuobj {
struct nvkm_object object;
struct nvkm_memory *memory;
const struct nvkm_gpuobj_func *func;
struct nvkm_gpuobj *parent;
struct nvkm_memory *memory;
struct nvkm_mm_node *node;
struct nvkm_mm heap;
u32 flags;
u64 addr;
u32 size;
struct nvkm_mm heap;
const struct nvkm_gpuobj_func *func;
void __iomem *map;
};
struct nvkm_gpuobj_func {
void (*acquire)(struct nvkm_gpuobj *);
void *(*acquire)(struct nvkm_gpuobj *);
void (*release)(struct nvkm_gpuobj *);
u32 (*rd32)(struct nvkm_gpuobj *, u32 offset);
void (*wr32)(struct nvkm_gpuobj *, u32 offset, u32 data);
};
int nvkm_gpuobj_new(struct nvkm_device *, u32 size, int align, bool zero,
struct nvkm_gpuobj *parent, struct nvkm_gpuobj **);
void nvkm_gpuobj_del(struct nvkm_gpuobj **);
static inline struct nvkm_gpuobj *
nv_gpuobj(void *obj)
{
......@@ -51,11 +54,8 @@ int nvkm_gpuobj_create_(struct nvkm_object *, struct nvkm_object *,
u32 flags, int length, void **);
void nvkm_gpuobj_destroy(struct nvkm_gpuobj *);
int nvkm_gpuobj_new(struct nvkm_object *, struct nvkm_object *, u32 size,
u32 align, u32 flags, struct nvkm_gpuobj **);
int nvkm_gpuobj_dup(struct nvkm_object *, struct nvkm_memory *,
struct nvkm_gpuobj **);
int nvkm_gpuobj_map_vm(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access,
int nvkm_gpuobj_wrap(struct nvkm_memory *, struct nvkm_gpuobj **);
int nvkm_gpuobj_map(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access,
struct nvkm_vma *);
void nvkm_gpuobj_unmap(struct nvkm_vma *);
......
......@@ -15,7 +15,7 @@ struct nvkm_dmaeng {
struct nvkm_engine engine;
/* creates a "physical" dma object from a struct nvkm_dmaobj */
int (*bind)(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
int (*bind)(struct nvkm_dmaobj *dmaobj, struct nvkm_gpuobj *parent,
struct nvkm_gpuobj **);
};
......
......@@ -141,7 +141,7 @@ nouveau_accel_fini(struct nouveau_drm *drm)
{
nouveau_channel_del(&drm->channel);
nvif_object_fini(&drm->ntfy);
nvkm_gpuobj_ref(NULL, &drm->notify);
nvkm_gpuobj_del(&drm->notify);
nvif_object_fini(&drm->nvsw);
nouveau_channel_del(&drm->cechan);
nvif_object_fini(&drm->ttm.copy);
......@@ -264,8 +264,8 @@ nouveau_accel_init(struct nouveau_drm *drm)
}
if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
ret = nvkm_gpuobj_new(nvxx_object(&drm->device.object), NULL, 32,
0, 0, &drm->notify);
ret = nvkm_gpuobj_new(nvxx_device(&drm->device), 32, 0, false,
NULL, &drm->notify);
if (ret) {
NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
nouveau_accel_fini(drm);
......
This diff is collapsed.
......@@ -24,32 +24,74 @@
#include "priv.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
struct hack {
struct nvkm_gpuobj object;
struct nvkm_gpuobj *parent;
};
static void
dtor(struct nvkm_object *object)
{
struct hack *hack = (void *)object;
nvkm_gpuobj_del(&hack->parent);
nvkm_object_destroy(&hack->object.object);
}
static struct nvkm_oclass
hack = {
.handle = NV_GPUOBJ_CLASS,
.ofuncs = &(struct nvkm_ofuncs) {
.dtor = dtor,
.init = _nvkm_object_init,
.fini = _nvkm_object_fini,
},
};
static int
nvkm_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
nvkm_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_gpuobj *pargpu,
struct nvkm_gpuobj **pgpuobj)
{
const struct nvkm_dmaeng_impl *impl = (void *)
nv_oclass(nv_object(dmaobj)->engine);
int ret = 0;
if (nv_object(dmaobj) == parent) { /* ctor bind */
if (&dmaobj->base == &pargpu->object) { /* ctor bind */
struct nvkm_object *parent = (void *)pargpu;
struct hack *object;
if (nv_mclass(parent->parent) == NV_DEVICE) {
/* delayed, or no, binding */
return 0;
}
ret = impl->bind(dmaobj, parent, pgpuobj);
if (ret == 0)
pargpu = (void *)nv_pclass((void *)pargpu, NV_GPUOBJ_CLASS);
ret = nvkm_object_create(parent, NULL, &hack, NV_GPUOBJ_CLASS, &object);
if (ret == 0) {
nvkm_object_ref(NULL, &parent);
*pgpuobj = &object->object;
ret = impl->bind(dmaobj, pargpu, &object->parent);
if (ret)
return ret;
object->object.node = object->parent->node;
object->object.addr = object->parent->addr;
object->object.size = object->parent->size;
return 0;
}
return ret;
}
return impl->bind(dmaobj, parent, pgpuobj);
return impl->bind(dmaobj, pargpu, pgpuobj);
}
int
......
......@@ -37,25 +37,14 @@ struct gf100_dmaobj {
};
static int
gf100_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
gf100_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_gpuobj *parent,
struct nvkm_gpuobj **pgpuobj)
{
struct gf100_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
struct nvkm_device *device = dmaobj->base.base.engine->subdev.device;
int ret;
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
switch (nv_mclass(parent->parent)) {
case GT214_DISP_CORE_CHANNEL_DMA:
case GT214_DISP_BASE_CHANNEL_DMA:
case GT214_DISP_OVERLAY_CHANNEL_DMA:
break;
default:
return -EINVAL;
}
} else
return 0;
ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
ret = nvkm_gpuobj_new(device, 24, 32, false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | nv_mclass(dmaobj));
......@@ -146,7 +135,7 @@ gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
break;
}
return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
return dmaeng->bind(&dmaobj->base, (void *)dmaobj, (void *)pobject);
}
static struct nvkm_ofuncs
......
......@@ -36,32 +36,14 @@ struct gf110_dmaobj {
};
static int
gf110_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
gf110_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_gpuobj *parent,
struct nvkm_gpuobj **pgpuobj)
{
struct gf110_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
struct nvkm_device *device = dmaobj->base.base.engine->subdev.device;
int ret;
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
switch (nv_mclass(parent->parent)) {
case GF110_DISP_CORE_CHANNEL_DMA:
case GK104_DISP_CORE_CHANNEL_DMA:
case GK110_DISP_CORE_CHANNEL_DMA:
case GM107_DISP_CORE_CHANNEL_DMA:
case GM204_DISP_CORE_CHANNEL_DMA:
case GF110_DISP_BASE_CHANNEL_DMA:
case GK104_DISP_BASE_CHANNEL_DMA:
case GK110_DISP_BASE_CHANNEL_DMA:
case GF110_DISP_OVERLAY_CONTROL_DMA:
case GK104_DISP_OVERLAY_CONTROL_DMA:
break;
default:
return -EINVAL;
}
} else
return 0;
ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
ret = nvkm_gpuobj_new(device, 24, 32, false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
......@@ -135,7 +117,7 @@ gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return -EINVAL;
}
return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
return dmaeng->bind(&dmaobj->base, (void *)dmaobj, (void *)pobject);
}
static struct nvkm_ofuncs
......
......@@ -37,41 +37,28 @@ struct nv04_dmaobj {
};
static int
nv04_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
nv04_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_gpuobj *parent,
struct nvkm_gpuobj **pgpuobj)
{
struct nv04_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
struct nvkm_gpuobj *gpuobj;
struct nvkm_device *device = dmaobj->base.base.engine->subdev.device;
u64 offset = dmaobj->base.start & 0xfffff000;
u64 adjust = dmaobj->base.start & 0x00000fff;
u32 length = dmaobj->base.limit - dmaobj->base.start;
int ret;
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
switch (nv_mclass(parent->parent)) {
case NV03_CHANNEL_DMA:
case NV10_CHANNEL_DMA:
case NV17_CHANNEL_DMA:
case NV40_CHANNEL_DMA:
break;
default:
return -EINVAL;
}
}
if (dmaobj->clone) {
struct nv04_mmu *mmu = nv04_mmu(dmaobj);
struct nvkm_memory *pgt = mmu->vm->pgt[0].mem[0];
if (!dmaobj->base.start)
return nvkm_gpuobj_dup(parent, pgt, pgpuobj);
return nvkm_gpuobj_wrap(pgt, pgpuobj);
nvkm_kmap(pgt);
offset = nvkm_ro32(pgt, 8 + (offset >> 10));
offset &= 0xfffff000;
nvkm_done(pgt);
}
ret = nvkm_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
*pgpuobj = gpuobj;
ret = nvkm_gpuobj_new(device, 16, 16, false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20));
......@@ -134,7 +121,7 @@ nv04_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return -EINVAL;
}
return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
return dmaeng->bind(&dmaobj->base, (void *)dmaobj, (void *)pobject);
}
static struct nvkm_ofuncs
......
......@@ -37,37 +37,14 @@ struct nv50_dmaobj {
};
static int
nv50_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
nv50_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_gpuobj *parent,
struct nvkm_gpuobj **pgpuobj)
{
struct nv50_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
struct nvkm_device *device = dmaobj->base.base.engine->subdev.device;
int ret;
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
switch (nv_mclass(parent->parent)) {
case NV40_CHANNEL_DMA:
case NV50_CHANNEL_GPFIFO:
case G82_CHANNEL_GPFIFO:
case NV50_DISP_CORE_CHANNEL_DMA:
case G82_DISP_CORE_CHANNEL_DMA:
case GT206_DISP_CORE_CHANNEL_DMA:
case GT200_DISP_CORE_CHANNEL_DMA:
case GT214_DISP_CORE_CHANNEL_DMA:
case NV50_DISP_BASE_CHANNEL_DMA:
case G82_DISP_BASE_CHANNEL_DMA:
case GT200_DISP_BASE_CHANNEL_DMA:
case GT214_DISP_BASE_CHANNEL_DMA:
case NV50_DISP_OVERLAY_CHANNEL_DMA:
case G82_DISP_OVERLAY_CHANNEL_DMA:
case GT200_DISP_OVERLAY_CHANNEL_DMA:
case GT214_DISP_OVERLAY_CHANNEL_DMA:
break;
default:
return -EINVAL;
}
}
ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
ret = nvkm_gpuobj_new(device, 24, 32, false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | nv_mclass(dmaobj));
......@@ -164,7 +141,7 @@ nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return -EINVAL;
}
return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
return dmaeng->bind(&dmaobj->base, (void *)dmaobj, (void *)pobject);
}
static struct nvkm_ofuncs
......
......@@ -22,7 +22,7 @@ int _nvkm_dmaeng_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_dmaeng_impl {
struct nvkm_oclass base;
struct nvkm_oclass *sclass;
int (*bind)(struct nvkm_dmaobj *, struct nvkm_object *,
int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *,
struct nvkm_gpuobj **);
};
#endif
......@@ -61,6 +61,7 @@ nvkm_fifo_channel_create_(struct nvkm_object *parent,
struct nvkm_handle *handle;
struct nvkm_dmaobj *dmaobj;
struct nvkm_fifo *fifo = (void *)engine;
struct nvkm_fifo_base *base = (void *)parent;
struct nvkm_fifo_chan *chan;
struct nvkm_dmaeng *dmaeng;
struct nvkm_subdev *subdev = &fifo->engine.subdev;
......@@ -91,7 +92,7 @@ nvkm_fifo_channel_create_(struct nvkm_object *parent,
return -EINVAL;
}
ret = dmaeng->bind(dmaobj, parent, &chan->pushgpu);
ret = dmaeng->bind(dmaobj, &base->gpuobj, &chan->pushgpu);
if (ret)
return ret;
}
......@@ -131,7 +132,7 @@ nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan)
fifo->channel[chan->chid] = NULL;
spin_unlock_irqrestore(&fifo->lock, flags);
nvkm_gpuobj_ref(NULL, &chan->pushgpu);
nvkm_gpuobj_del(&chan->pushgpu);
nvkm_namedb_destroy(&chan->namedb);
}
......
......@@ -140,6 +140,7 @@ g84_fifo_object_attach(struct nvkm_object *parent,
else
context = 0x00000004; /* just non-zero */
if (object->engine) {
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_DMAOBJ:
case NVDEV_ENGINE_SW : context |= 0x00000000; break;
......@@ -158,6 +159,7 @@ g84_fifo_object_attach(struct nvkm_object *parent,
default:
return -EINVAL;
}
}
return nvkm_ramht_insert(chan->ramht, 0, handle, context);
}
......@@ -374,6 +376,7 @@ g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_device *device = nv_engine(engine)->subdev.device;
struct nv50_fifo_base *base;
int ret;
......@@ -383,13 +386,13 @@ g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
ret = nvkm_gpuobj_new(device, 0x0200, 0, true, &base->base.gpuobj,
&base->eng);
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
0, &base->pgd);
ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj,
&base->pgd);
if (ret)
return ret;
......@@ -397,13 +400,13 @@ g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, &base->base.gpuobj,
&base->cache);
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, &base->base.gpuobj,
&base->ramfc);
if (ret)
return ret;
......
......@@ -130,7 +130,7 @@ gf100_fifo_context_attach(struct nvkm_object *parent,
}
if (!ectx->vma.node) {
ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
ret = nvkm_gpuobj_map(nv_gpuobj(ectx), base->vm,
NV_MEM_ACCESS_RW, &ectx->vma);
if (ret)
return ret;
......@@ -334,6 +334,7 @@ gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_device *device = nv_engine(engine)->subdev.device;
struct gf100_fifo_base *base;
int ret;
......@@ -344,8 +345,7 @@ gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
&base->pgd);
ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &base->pgd);
if (ret)
return ret;
......@@ -368,7 +368,7 @@ gf100_fifo_context_dtor(struct nvkm_object *object)
{
struct gf100_fifo_base *base = (void *)object;
nvkm_vm_ref(NULL, &base->vm, base->pgd);
nvkm_gpuobj_ref(NULL, &base->pgd);
nvkm_gpuobj_del(&base->pgd);
nvkm_fifo_context_destroy(&base->base);
}
......
......@@ -154,7 +154,7 @@ gk104_fifo_context_attach(struct nvkm_object *parent,
}
if (!ectx->vma.node) {
ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
ret = nvkm_gpuobj_map(nv_gpuobj(ectx), base->vm,
NV_MEM_ACCESS_RW, &ectx->vma);
if (ret)
return ret;
......@@ -388,6 +388,7 @@ gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_device *device = nv_engine(engine)->subdev.device;
struct gk104_fifo_base *base;
int ret;
......@@ -397,8 +398,7 @@ gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
&base->pgd);
ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &base->pgd);
if (ret)
return ret;
......@@ -421,7 +421,7 @@ gk104_fifo_context_dtor(struct nvkm_object *object)
{
struct gk104_fifo_base *base = (void *)object;
nvkm_vm_ref(NULL, &base->vm, base->pgd);
nvkm_gpuobj_ref(NULL, &base->pgd);
nvkm_gpuobj_del(&base->pgd);
nvkm_fifo_context_destroy(&base->base);
}
......
......@@ -65,6 +65,7 @@ nv04_fifo_object_attach(struct nvkm_object *parent,
else
context = 0x00000004; /* just non-zero */
if (object->engine) {
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_DMAOBJ:
case NVDEV_ENGINE_SW:
......@@ -79,6 +80,7 @@ nv04_fifo_object_attach(struct nvkm_object *parent,
default:
return -EINVAL;
}
}
context |= 0x80000000; /* valid */
context |= chid << 24;
......
......@@ -78,6 +78,7 @@ nv40_fifo_object_attach(struct nvkm_object *parent,
else
context = 0x00000004; /* just non-zero */
if (object->engine) {
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_DMAOBJ:
case NVDEV_ENGINE_SW:
......@@ -92,6 +93,7 @@ nv40_fifo_object_attach(struct nvkm_object *parent,
default:
return -EINVAL;
}
}
context |= chid << 23;
......
......@@ -171,6 +171,7 @@ nv50_fifo_object_attach(struct nvkm_object *parent,
else
context = 0x00000004; /* just non-zero */
if (object->engine) {
switch (nv_engidx(object->engine)) {
case NVDEV_ENGINE_DMAOBJ:
case NVDEV_ENGINE_SW : context |= 0x00000000; break;
......@@ -179,6 +180,7 @@ nv50_fifo_object_attach(struct nvkm_object *parent,
default:
return -EINVAL;
}
}
return nvkm_ramht_insert(chan->ramht, 0, handle, context);
}
......@@ -402,6 +404,7 @@ nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_device *device = nv_engine(engine)->subdev.device;
struct nv50_fifo_base *base;
int ret;
......@@ -411,17 +414,17 @@ nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200,
0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, &base->base.gpuobj,
&base->ramfc);
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0,
NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
ret = nvkm_gpuobj_new(device, 0x1200, 0, true, &base->base.gpuobj,
&base->eng);
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0,
ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj,
&base->pgd);
if (ret)
return ret;
......@@ -438,10 +441,10 @@ nv50_fifo_context_dtor(struct nvkm_object *object)
{
struct nv50_fifo_base *base = (void *)object;
nvkm_vm_ref(NULL, &base->vm, base->pgd);
nvkm_gpuobj_ref(NULL, &base->pgd);
nvkm_gpuobj_ref(NULL, &base->eng);
nvkm_gpuobj_ref(NULL, &base->ramfc);
nvkm_gpuobj_ref(NULL, &base->cache);
nvkm_gpuobj_del(&base->pgd);
nvkm_gpuobj_del(&base->eng);
nvkm_gpuobj_del(&base->ramfc);
nvkm_gpuobj_del(&base->cache);
nvkm_fifo_context_destroy(&base->base);
}
......
......@@ -75,8 +75,7 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x8000, 0, 0,
&bar_vm->pgd);
ret = nvkm_gpuobj_new(device, 0x8000, 0, false, NULL, &bar_vm->pgd);
if (ret)
return ret;
......@@ -157,14 +156,14 @@ gf100_bar_dtor(struct nvkm_object *object)
struct gf100_bar *bar = (void *)object;
nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd);
nvkm_gpuobj_ref(NULL, &bar->bar[1].pgd);
nvkm_gpuobj_del(&bar->bar[1].pgd);
nvkm_memory_del(&bar->bar[1].mem);
if (bar->bar[0].vm) {
nvkm_memory_del(&bar->bar[0].vm->pgt[0].mem[0]);
nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd);
}
nvkm_gpuobj_ref(NULL, &bar->bar[0].pgd);
nvkm_gpuobj_del(&bar->bar[0].pgd);
nvkm_memory_del(&bar->bar[0].mem);
nvkm_bar_destroy(&bar->base);
......
......@@ -99,7 +99,6 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
static struct lock_class_key bar1_lock;
static struct lock_class_key bar3_lock;
struct nvkm_device *device = nv_device(parent);
struct nvkm_object *heap;
struct nvkm_vm *vm;
struct nv50_bar *bar;
u64 start, limit;
......@@ -110,19 +109,17 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x20000, 0,
NVOBJ_FLAG_HEAP, &bar->mem);
heap = nv_object(bar->mem);
ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem);
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(bar), heap,
(device->chipset == 0x50) ? 0x1400 : 0x0200,
0, 0, &bar->pad);
ret = nvkm_gpuobj_new(device, (device->chipset == 0x50) ?
0x1400 : 0x200, 0, false, bar->mem,
&bar->pad);
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(bar), heap, 0x4000, 0, 0, &bar->pgd);
ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd);
if (ret)
return ret;
......@@ -145,7 +142,7 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(bar), heap, 24, 16, 0, &bar->bar3);
ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar3);
if (ret)
return ret;
......@@ -174,7 +171,7 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_gpuobj_new(nv_object(bar), heap, 24, 16, 0, &bar->bar1);
ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1);
if (ret)
return ret;
......@@ -203,16 +200,16 @@ static void
nv50_bar_dtor(struct nvkm_object *object)
{
struct nv50_bar *bar = (void *)object;
nvkm_gpuobj_ref(NULL, &bar->bar1);
nvkm_gpuobj_del(&bar->bar1);
nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);
nvkm_gpuobj_ref(NULL, &bar->bar3);
nvkm_gpuobj_del(&bar->bar3);
if (bar->bar3_vm) {
nvkm_memory_del(&bar->bar3_vm->pgt[0].mem[0]);
nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd);
}
nvkm_gpuobj_ref(NULL, &bar->pgd);
nvkm_gpuobj_ref(NULL, &bar->pad);
nvkm_gpuobj_ref(NULL, &bar->mem);
nvkm_gpuobj_del(&bar->pgd);
nvkm_gpuobj_del(&bar->pad);
nvkm_gpuobj_del(&bar->mem);
nvkm_bar_destroy(&bar->base);
}
......
......@@ -420,7 +420,7 @@ nvkm_vm_link(struct nvkm_vm *vm, struct nvkm_gpuobj *pgd)
if (!vpgd)
return -ENOMEM;
nvkm_gpuobj_ref(pgd, &vpgd->obj);
vpgd->obj = pgd;
mutex_lock(&vm->mutex);
for (i = vm->fpde; i <= vm->lpde; i++)
......@@ -434,7 +434,6 @@ static void
nvkm_vm_unlink(struct nvkm_vm *vm, struct nvkm_gpuobj *mpgd)
{
struct nvkm_vm_pgd *vpgd, *tmp;
struct nvkm_gpuobj *pgd = NULL;
if (!mpgd)
return;
......@@ -442,15 +441,12 @@ nvkm_vm_unlink(struct nvkm_vm *vm, struct nvkm_gpuobj *mpgd)
mutex_lock(&vm->mutex);
list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
if (vpgd->obj == mpgd) {
pgd = vpgd->obj;
list_del(&vpgd->head);
kfree(vpgd);
break;
}
}
mutex_unlock(&vm->mutex);
nvkm_gpuobj_ref(NULL, &pgd);
}
static void
......
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