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Commit f05d6717 authored by Peter Zijlstra's avatar Peter Zijlstra
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Merge branch 'locking/header'

parents c84d5305 459e3953
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Showing with 3 additions and 42 deletions
arch/alpha/include/asm/atomic.h
View file @ f05d6717
...@@ -24,7 +24,6 @@ ...@@ -24,7 +24,6 @@
#define __atomic_acquire_fence() #define __atomic_acquire_fence()
#define __atomic_post_full_fence() #define __atomic_post_full_fence()
#define ATOMIC_INIT(i) { (i) }
#define ATOMIC64_INIT(i) { (i) } #define ATOMIC64_INIT(i) { (i) }
#define atomic_read(v) READ_ONCE((v)->counter) #define atomic_read(v) READ_ONCE((v)->counter)
......
arch/arc/include/asm/atomic.h
View file @ f05d6717
...@@ -14,8 +14,6 @@ ...@@ -14,8 +14,6 @@
#include <asm/barrier.h> #include <asm/barrier.h>
#include <asm/smp.h> #include <asm/smp.h>
#define ATOMIC_INIT(i) { (i) }
#ifndef CONFIG_ARC_PLAT_EZNPS #ifndef CONFIG_ARC_PLAT_EZNPS
#define atomic_read(v) READ_ONCE((v)->counter) #define atomic_read(v) READ_ONCE((v)->counter)
......
arch/arm/include/asm/atomic.h
View file @ f05d6717
...@@ -15,8 +15,6 @@ ...@@ -15,8 +15,6 @@
#include <asm/barrier.h> #include <asm/barrier.h>
#include <asm/cmpxchg.h> #include <asm/cmpxchg.h>
#define ATOMIC_INIT(i) { (i) }
#ifdef __KERNEL__ #ifdef __KERNEL__
/* /*
......
arch/arm64/include/asm/atomic.h
View file @ f05d6717
...@@ -99,8 +99,6 @@ static inline long arch_atomic64_dec_if_positive(atomic64_t *v) ...@@ -99,8 +99,6 @@ static inline long arch_atomic64_dec_if_positive(atomic64_t *v)
return __lse_ll_sc_body(atomic64_dec_if_positive, v); return __lse_ll_sc_body(atomic64_dec_if_positive, v);
} }
#define ATOMIC_INIT(i) { (i) }
#define arch_atomic_read(v) __READ_ONCE((v)->counter) #define arch_atomic_read(v) __READ_ONCE((v)->counter)
#define arch_atomic_set(v, i) __WRITE_ONCE(((v)->counter), (i)) #define arch_atomic_set(v, i) __WRITE_ONCE(((v)->counter), (i))
......
arch/h8300/include/asm/atomic.h
View file @ f05d6717
...@@ -12,8 +12,6 @@ ...@@ -12,8 +12,6 @@
* resource counting etc.. * resource counting etc..
*/ */
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) READ_ONCE((v)->counter) #define atomic_read(v) READ_ONCE((v)->counter)
#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
......
arch/hexagon/include/asm/atomic.h
View file @ f05d6717
...@@ -12,8 +12,6 @@ ...@@ -12,8 +12,6 @@
#include <asm/cmpxchg.h> #include <asm/cmpxchg.h>
#include <asm/barrier.h> #include <asm/barrier.h>
#define ATOMIC_INIT(i) { (i) }
/* Normal writes in our arch don't clear lock reservations */ /* Normal writes in our arch don't clear lock reservations */
static inline void atomic_set(atomic_t *v, int new) static inline void atomic_set(atomic_t *v, int new)
......
arch/ia64/include/asm/atomic.h
View file @ f05d6717
...@@ -19,7 +19,6 @@ ...@@ -19,7 +19,6 @@
#include <asm/barrier.h> #include <asm/barrier.h>
#define ATOMIC_INIT(i) { (i) }
#define ATOMIC64_INIT(i) { (i) } #define ATOMIC64_INIT(i) { (i) }
#define atomic_read(v) READ_ONCE((v)->counter) #define atomic_read(v) READ_ONCE((v)->counter)
......
arch/m68k/include/asm/atomic.h
View file @ f05d6717
...@@ -16,8 +16,6 @@ ...@@ -16,8 +16,6 @@
* We do not have SMP m68k systems, so we don't have to deal with that. * We do not have SMP m68k systems, so we don't have to deal with that.
*/ */
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) READ_ONCE((v)->counter) #define atomic_read(v) READ_ONCE((v)->counter)
#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
......
arch/mips/include/asm/atomic.h
View file @ f05d6717
...@@ -45,7 +45,6 @@ static __always_inline type pfx##_xchg(pfx##_t *v, type n) \ ...@@ -45,7 +45,6 @@ static __always_inline type pfx##_xchg(pfx##_t *v, type n) \
return xchg(&v->counter, n); \ return xchg(&v->counter, n); \
} }
#define ATOMIC_INIT(i) { (i) }
ATOMIC_OPS(atomic, int) ATOMIC_OPS(atomic, int)
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
......
arch/parisc/include/asm/atomic.h
View file @ f05d6717
...@@ -136,8 +136,6 @@ ATOMIC_OPS(xor, ^=) ...@@ -136,8 +136,6 @@ ATOMIC_OPS(xor, ^=)
#undef ATOMIC_OP_RETURN #undef ATOMIC_OP_RETURN
#undef ATOMIC_OP #undef ATOMIC_OP
#define ATOMIC_INIT(i) { (i) }
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
#define ATOMIC64_INIT(i) { (i) } #define ATOMIC64_INIT(i) { (i) }
......
arch/powerpc/include/asm/atomic.h
View file @ f05d6717
...@@ -11,8 +11,6 @@ ...@@ -11,8 +11,6 @@
#include <asm/cmpxchg.h> #include <asm/cmpxchg.h>
#include <asm/barrier.h> #include <asm/barrier.h>
#define ATOMIC_INIT(i) { (i) }
/* /*
* Since *_return_relaxed and {cmp}xchg_relaxed are implemented with * Since *_return_relaxed and {cmp}xchg_relaxed are implemented with
* a "bne-" instruction at the end, so an isync is enough as a acquire barrier * a "bne-" instruction at the end, so an isync is enough as a acquire barrier
......
arch/riscv/include/asm/atomic.h
View file @ f05d6717
...@@ -19,8 +19,6 @@ ...@@ -19,8 +19,6 @@
#include <asm/cmpxchg.h> #include <asm/cmpxchg.h>
#include <asm/barrier.h> #include <asm/barrier.h>
#define ATOMIC_INIT(i) { (i) }
#define __atomic_acquire_fence() \ #define __atomic_acquire_fence() \
__asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory")
......
arch/s390/include/asm/atomic.h
View file @ f05d6717
...@@ -15,8 +15,6 @@ ...@@ -15,8 +15,6 @@
#include <asm/barrier.h> #include <asm/barrier.h>
#include <asm/cmpxchg.h> #include <asm/cmpxchg.h>
#define ATOMIC_INIT(i) { (i) }
static inline int atomic_read(const atomic_t *v) static inline int atomic_read(const atomic_t *v)
{ {
int c; int c;
......
arch/sh/include/asm/atomic.h
View file @ f05d6717
...@@ -19,8 +19,6 @@ ...@@ -19,8 +19,6 @@
#include <asm/cmpxchg.h> #include <asm/cmpxchg.h>
#include <asm/barrier.h> #include <asm/barrier.h>
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) READ_ONCE((v)->counter) #define atomic_read(v) READ_ONCE((v)->counter)
#define atomic_set(v,i) WRITE_ONCE((v)->counter, (i)) #define atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
......
arch/sparc/include/asm/atomic_32.h
View file @ f05d6717
...@@ -18,8 +18,6 @@ ...@@ -18,8 +18,6 @@
#include <asm/barrier.h> #include <asm/barrier.h>
#include <asm-generic/atomic64.h> #include <asm-generic/atomic64.h>
#define ATOMIC_INIT(i) { (i) }
int atomic_add_return(int, atomic_t *); int atomic_add_return(int, atomic_t *);
int atomic_fetch_add(int, atomic_t *); int atomic_fetch_add(int, atomic_t *);
int atomic_fetch_and(int, atomic_t *); int atomic_fetch_and(int, atomic_t *);
......
arch/sparc/include/asm/atomic_64.h
View file @ f05d6717
...@@ -12,7 +12,6 @@ ...@@ -12,7 +12,6 @@
#include <asm/cmpxchg.h> #include <asm/cmpxchg.h>
#include <asm/barrier.h> #include <asm/barrier.h>
#define ATOMIC_INIT(i) { (i) }
#define ATOMIC64_INIT(i) { (i) } #define ATOMIC64_INIT(i) { (i) }
#define atomic_read(v) READ_ONCE((v)->counter) #define atomic_read(v) READ_ONCE((v)->counter)
......
arch/x86/include/asm/atomic.h
View file @ f05d6717
...@@ -14,8 +14,6 @@ ...@@ -14,8 +14,6 @@
* resource counting etc.. * resource counting etc..
*/ */
#define ATOMIC_INIT(i) { (i) }
/** /**
* arch_atomic_read - read atomic variable * arch_atomic_read - read atomic variable
* @v: pointer of type atomic_t * @v: pointer of type atomic_t
......
arch/xtensa/include/asm/atomic.h
View file @ f05d6717
...@@ -19,8 +19,6 @@ ...@@ -19,8 +19,6 @@
#include <asm/cmpxchg.h> #include <asm/cmpxchg.h>
#include <asm/barrier.h> #include <asm/barrier.h>
#define ATOMIC_INIT(i) { (i) }
/* /*
* This Xtensa implementation assumes that the right mechanism * This Xtensa implementation assumes that the right mechanism
* for exclusion is for locking interrupts to level EXCM_LEVEL. * for exclusion is for locking interrupts to level EXCM_LEVEL.
......
include/asm-generic/atomic.h
View file @ f05d6717
...@@ -159,8 +159,6 @@ ATOMIC_OP(xor, ^) ...@@ -159,8 +159,6 @@ ATOMIC_OP(xor, ^)
* resource counting etc.. * resource counting etc..
*/ */
#define ATOMIC_INIT(i) { (i) }
/** /**
* atomic_read - read atomic variable * atomic_read - read atomic variable
* @v: pointer of type atomic_t * @v: pointer of type atomic_t
......
include/asm-generic/qspinlock.h
View file @ f05d6717
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
#define __ASM_GENERIC_QSPINLOCK_H #define __ASM_GENERIC_QSPINLOCK_H
#include <asm-generic/qspinlock_types.h> #include <asm-generic/qspinlock_types.h>
#include <linux/atomic.h>
/** /**
* queued_spin_is_locked - is the spinlock locked? * queued_spin_is_locked - is the spinlock locked?
......
include/asm-generic/qspinlock_types.h
View file @ f05d6717
...@@ -9,15 +9,7 @@ ...@@ -9,15 +9,7 @@
#ifndef __ASM_GENERIC_QSPINLOCK_TYPES_H #ifndef __ASM_GENERIC_QSPINLOCK_TYPES_H
#define __ASM_GENERIC_QSPINLOCK_TYPES_H #define __ASM_GENERIC_QSPINLOCK_TYPES_H
/*
* Including atomic.h with PARAVIRT on will cause compilation errors because
* of recursive header file incluson via paravirt_types.h. So don't include
* it if PARAVIRT is on.
*/
#ifndef CONFIG_PARAVIRT
#include <linux/types.h> #include <linux/types.h>
#include <linux/atomic.h>
#endif
typedef struct qspinlock { typedef struct qspinlock {
union { union {
......
include/linux/types.h
View file @ f05d6717
...@@ -167,6 +167,8 @@ typedef struct { ...@@ -167,6 +167,8 @@ typedef struct {
int counter; int counter;
} atomic_t; } atomic_t;
#define ATOMIC_INIT(i) { (i) }
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
typedef struct { typedef struct {
s64 counter; s64 counter;
......
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