Commit f0b3c84e authored by Deepak Saxena's avatar Deepak Saxena Committed by Deepak Saxena

[ARM] Remove ADIFCC machine type

The code is completely out of date, I am no longer maintaining it, 
and nobdy has volunteered to do so; therefore, I am killing it.
Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
parent d0b53c03
......@@ -72,9 +72,6 @@ choice
prompt "ARM system type"
default ARCH_RPC
config ARCH_ADIFCC
bool "ADIFCC-based"
config ARCH_CLPS7500
bool "Cirrus-CL-PS7500FE"
......
......@@ -91,7 +91,6 @@ textaddr-$(CONFIG_ARCH_CLPS711X) := 0xc0028000
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000
machine-$(CONFIG_ARCH_IOP3XX) := iop3xx
machine-$(CONFIG_ARCH_ADIFCC) := adifcc
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
machine-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410
......
......@@ -49,8 +49,6 @@ initrd_phys-$(CONFIG_ARCH_SA1100) := 0xc0800000
zreladdr-$(CONFIG_ARCH_PXA) := 0xa0008000
zreladdr-$(CONFIG_ARCH_IOP3XX) := 0xa0008000
params_phys-$(CONFIG_ARCH_IOP3XX) := 0xa0000100
zreladdr-$(CONFIG_ARCH_ADIFCC) := 0xc0008000
params_phys-$(CONFIG_ARCH_ADIFCC) := 0xc0000100
zreladdr-$(CONFIG_ARCH_IXP4XX) := 0x00008000
params-phys-$(CONFIG_ARCH_IXP4XX) := 0x00000100
zreladdr-$(CONFIG_ARCH_OMAP) := 0x10008000
......
......@@ -66,7 +66,4 @@ __XScale_start:
mov r7, #MACH_TYPE_IQ80310
#endif
#ifdef CONFIG_ARCH_ADI_EVB
mov r7, #MACH_TYPE_ADI_EVB
#endif
This diff is collapsed.
......@@ -439,32 +439,6 @@
#endif
.endm
#elif defined(CONFIG_ARCH_ADI_EVB)
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
mov \rx, #0x00400000 @ physical base address
orrne \rx, \rx, #0xff000000 @ virtual base
.endm
.macro senduart,rd,rx
strb \rd, [\rx]
.endm
.macro busyuart,rd,rx
1002: ldrb \rd, [\rx, #0x5]
and \rd, \rd, #0x60
teq \rd, #0x60
bne 1002b
.endm
.macro waituart,rd,rx
1001: ldrb \rd, [\rx, #0x6]
tst \rd, #0x10
beq 1001b
.endm
#elif defined(CONFIG_ARCH_IXP4XX)
.macro addruart,rx
......
......@@ -561,7 +561,7 @@ ENTRY(soft_irq_mask)
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_IOP310) || defined(CONFIG_ARCH_ADIFCC)
#elif defined(CONFIG_ARCH_IOP310)
.macro disable_fiq
.endm
......
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := arch.o irq.o mm.o
obj-m :=
obj-n :=
obj- :=
/*
* linux/arch/arm/mach-adifcc/arch.c
*
* Copyright (C) 2001 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/fs.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
extern void adifcc_map_io(void);
extern void adifcc_init_irq(void);
#ifdef CONFIG_ARCH_ADI_EVB
MACHINE_START(ADI_EVB, "ADI 80200FCC Evaluation Board")
MAINTAINER("MontaVista Software Inc.")
BOOT_MEM(0xc0000000, 0x00400000, 0xff400000)
MAPIO(adifcc_map_io)
INITIRQ(adifcc_init_irq)
MACHINE_END
#endif
/*
* linux/arch/arm/mach-xscale/irq.c
*
* Author: Deepak Saxena
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Based on IOP80310 code. Currently there's nothing more than the
* 80200 on chip interrupts. That'll change once the hardware adds
* support for PCI though.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/hardware.h>
static void xs80200_irq_mask (unsigned int irq)
{
long INTCTL;
asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (INTCTL));
switch (irq) {
case IRQ_XS80200_BCU: INTCTL &= ~(1<<3); break;
case IRQ_XS80200_PMU: INTCTL &= ~(1<<2); break;
case IRQ_XS80200_EXTIRQ: INTCTL &= ~(1<<1); break;
case IRQ_XS80200_EXTFIQ: INTCTL &= ~(1<<0); break;
}
asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (INTCTL));
}
static void xs80200_irq_unmask (unsigned int irq)
{
long INTCTL;
asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (INTCTL));
switch (irq) {
case IRQ_XS80200_BCU: INTCTL |= (1<<3); break;
case IRQ_XS80200_PMU: INTCTL |= (1<<2); break;
case IRQ_XS80200_EXTIRQ: INTCTL |= (1<<1); break;
case IRQ_XS80200_EXTFIQ: INTCTL |= (1<<0); break;
}
asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (INTCTL));
}
void __init adifcc_init_irq(void)
{
int i;
for (i = 0; i < NR_XS80200_IRQS; i++) {
irq_desc[i].valid = 1;
irq_desc[i].probe_ok = 0;
irq_desc[i].mask_ack = xs80200_irq_mask;
irq_desc[i].mask = xs80200_irq_mask;
irq_desc[i].unmask = xs80200_irq_unmask;
}
}
/*
* linux/arch/arm/mach-xscale/mm.c
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
static struct map_desc adifcc_io_desc[] __initdata = {
/* on-board devices */
{ 0xff400000, 0x00400000, 0x00300000, MT_DEVICE }
};
void __init adifcc_map_io(void)
{
iotable_init(adifcc_io_desc, ARRAY_SIZE(adifcc_io_desc));
}
......@@ -220,7 +220,7 @@ config CPU_SA1100
# XScale
config CPU_XSCALE
bool
depends on ARCH_IOP3XX || ARCH_ADIFCC || ARCH_PXA || ARCH_IXP4XX
depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX
default y
select CPU_32v5
select CPU_ABRT_EV5T
......
/*
* linux/include/asm/arch-80200fcc/adi_evb.h
*
* ADI 80200FCC evaluation board definitions
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#define ADI_EVB__RAMBASE 0xa0000000
#define ADI_EVB__UART 0x00400000 /* UART */
#define ADI_EVB_7SEG_1 0x00500000 /* 7-Segment */
/*
* linux/include/asm-arm/arch-80200fcc/dma.h
*
* Copyright (C) 2001 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#define MAX_DMA_ADDRESS 0xffffffff
/* No DMA */
#define MAX_DMA_CHANNELS 0
#endif /* _ASM_ARCH_DMA_H */
/*
* linux/include/asm-arm/arch-adifcc/hardware.h
*
* Hardware definitions for ADI based systems
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright (C) 2000-2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <linux/config.h>
#define PCIO_BASE 0
#if defined(CONFIG_ARCH_ADI_EVB)
#include "adi_evb.h"
#endif
#endif /* _ASM_ARCH_HARDWARE_H */
/*
* linux/include/asm-arm/arch-adifcc/io.h
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright (C) 2001 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) (PCIO_BASE + (a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#endif
/*
* linux/include/asm-arm/arch-80200fcc/irqs.h
*
* Author: Deepak Saxena <dsaxena@mvista.com>
* Copyright: (C) 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define IRQ_XS80200_BCU 0 /* Bus Control Unit */
#define IRQ_XS80200_PMU 1 /* Performance Monitoring Unit */
#define IRQ_XS80200_EXTIRQ 2 /* external IRQ signal */
#define IRQ_XS80200_EXTFIQ 3 /* external IRQ signal */
#define NR_XS80200_IRQS 4
#define NR_IRQS NR_XS80200_IRQS
#define IRQ_XSCALE_PMU IRQ_XS80200_PMU
/*
* linux/include/asm-arm/arch-adifcc/memory.h
*
* Copyright (c) 2001 MontaVista Software, Inc.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0xC0000000UL)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*
* These are dummies for now.
*/
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif
/*
* linux/include/asm-arm/arch-adifcc/param.h
*/
/*
* include/asm-arm/arch-adifcc/serial.h
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright (c) 2001 MontaVista Software, Inc.
*/
#include <linux/config.h>
/*
* This assumes you have a 1.8432 MHz clock for your UART.
*
* It'd be nice if someone built a serial card with a 24.576 MHz
* clock, since the 16550A is capable of handling a top speed of 1.5
* megabits/second; but this requires the faster clock.
*/
#define BASE_BAUD ( 1852000 / 16 )
/* Standard COM flags */
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#ifdef CONFIG_ARCH_ADI_EVB
/*
* One serial port, int goes to FIQ, so we run in polled mode
*/
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0xff400000, 0, STD_COM_FLAGS } /* ttyS0 */
#define EXTRA_SERIAL_PORT_DEFNS
#endif
/*
* linux/include/asm-arm/arch-adifcc/system.h
*
* Copyright (C) 2001 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
static inline void arch_idle(void)
{
#if 0
cpu_do_idle();
#endif
}
static inline void arch_reset(char mode)
{
if ( 1 && mode == 's') {
/* Jump into ROM at address 0 */
cpu_reset(0);
} else {
/* Use on-chip reset capability */
}
}
/*
* linux/include/asm-arm/arch-adifcc/timex.h
*
* XScale architecture timex specifications
*/
/* This is for a timer based on the XS80200's PMU counter */
#define CLOCK_TICK_RATE 600000000 /* Underlying HZ */
/*
* linux/include/asm-arm/arch-adifcc/uncompress.h
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright (c) 2001 MontaVista Software, Inc.
*
*/
#define UART_BASE ((volatile unsigned char *)0x00400000)
static __inline__ void putc(char c)
{
while ((UART_BASE[5] & 0x60) != 0x60);
UART_BASE[0] = c;
}
/*
* This does not append a newline
*/
static void puts(const char *s)
{
while (*s) {
putc(*s);
if (*s == '\n')
putc('\r');
s++;
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
/*
* linux/include/asm-arm/arch-adifcc/vmalloc.h
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (0xe8000000)
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