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Commit f0b83cc8 authored by Juergen Beisert's avatar Juergen Beisert Committed by Jonathan Cameron
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Staging/iio/adc/touchscreen/MXS: simplify register access 

Replace the individual register access by a few shared access function to make the
code easier to read and in order to add the i.MX23 SoC in the next step.
Signed-off-by: default avatarJuergen Beisert <jbe@pengutronix.de>
Tested-by: default avatarMarek Vasut <marex@denx.de>
Acked-by: default avatarMarek Vasut <marex@denx.de>
Tested-by: default avatarLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>

CC: linux-arm-kernel@lists.infradead.org
CC: linux-input@vger.kernel.org
CC: devel@driverdev.osuosl.org
CC: Marek Vasut <marex@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
parent 7e4d4a6f
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Showing with 120 additions and 84 deletions
drivers/staging/iio/adc/mxs-lradc.c
View file @ f0b83cc8
...@@ -238,6 +238,56 @@ struct mxs_lradc { ...@@ -238,6 +238,56 @@ struct mxs_lradc {
#define LRADC_RESOLUTION 12 #define LRADC_RESOLUTION 12
#define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1) #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
{
writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
}
static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
{
writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
}
static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
{
writel(val, lradc->base + reg);
}
static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
{
return LRADC_CTRL0_MX28_PLATE_MASK;
}
static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
{
return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
}
static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
{
return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
}
static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
{
return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
}
static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
{
return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
}
static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
{
return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
}
static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
{
return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
}
/* /*
* Raw I/O operations * Raw I/O operations
*/ */
...@@ -272,21 +322,19 @@ static int mxs_lradc_read_raw(struct iio_dev *iio_dev, ...@@ -272,21 +322,19 @@ static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
* Virtual channel 0 is always used here as the others are always not * Virtual channel 0 is always used here as the others are always not
* used if doing raw sampling. * used if doing raw sampling.
*/ */
writel(LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK, mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); LRADC_CTRL1);
writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
/* Clean the slot's previous content, then set new one. */ /* Clean the slot's previous content, then set new one. */
writel(LRADC_CTRL4_LRADCSELECT_MASK(0), mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0), LRADC_CTRL4);
lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); mxs_lradc_reg_set(lradc, chan->channel, LRADC_CTRL4);
writel(chan->channel, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
writel(0, lradc->base + LRADC_CH(0)); mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
/* Enable the IRQ and start sampling the channel. */ /* Enable the IRQ and start sampling the channel. */
writel(LRADC_CTRL1_LRADC_IRQ_EN(0), mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); mxs_lradc_reg_set(lradc, 1 << 0, LRADC_CTRL0);
writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
/* Wait for completion on the channel, 1 second max. */ /* Wait for completion on the channel, 1 second max. */
ret = wait_for_completion_killable_timeout(&lradc->completion, HZ); ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
...@@ -300,8 +348,7 @@ static int mxs_lradc_read_raw(struct iio_dev *iio_dev, ...@@ -300,8 +348,7 @@ static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
ret = IIO_VAL_INT; ret = IIO_VAL_INT;
err: err:
writel(LRADC_CTRL1_LRADC_IRQ_EN(0), mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
mutex_unlock(&lradc->lock); mutex_unlock(&lradc->lock);
...@@ -327,10 +374,9 @@ static int mxs_lradc_ts_touched(struct mxs_lradc *lradc) ...@@ -327,10 +374,9 @@ static int mxs_lradc_ts_touched(struct mxs_lradc *lradc)
uint32_t reg; uint32_t reg;
/* Enable touch detection. */ /* Enable touch detection. */
writel(LRADC_CTRL0_MX28_PLATE_MASK, mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
writel(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE, LRADC_CTRL0);
lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
msleep(LRADC_TS_SAMPLE_DELAY_MS); msleep(LRADC_TS_SAMPLE_DELAY_MS);
...@@ -375,32 +421,33 @@ static int32_t mxs_lradc_ts_sample(struct mxs_lradc *lradc, ...@@ -375,32 +421,33 @@ static int32_t mxs_lradc_ts_sample(struct mxs_lradc *lradc,
*/ */
switch (plate) { switch (plate) {
case LRADC_SAMPLE_X: case LRADC_SAMPLE_X:
ctrl0 = LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW; ctrl0 = mxs_lradc_drive_x_plate(lradc);
chan = 3; chan = 3;
break; break;
case LRADC_SAMPLE_Y: case LRADC_SAMPLE_Y:
ctrl0 = LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW; ctrl0 = mxs_lradc_drive_y_plate(lradc);
chan = 4; chan = 4;
break; break;
case LRADC_SAMPLE_PRESSURE: case LRADC_SAMPLE_PRESSURE:
ctrl0 = LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW; ctrl0 = mxs_lradc_drive_pressure(lradc);
chan = 5; chan = 5;
break; break;
} }
if (change) { if (change) {
writel(LRADC_CTRL0_MX28_PLATE_MASK, mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc),
lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); LRADC_CTRL0);
writel(ctrl0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); mxs_lradc_reg_set(lradc, ctrl0, LRADC_CTRL0);
writel(LRADC_CTRL4_LRADCSELECT_MASK(slot), mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(slot),
lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); LRADC_CTRL4);
writel(chan << LRADC_CTRL4_LRADCSELECT_OFFSET(slot), mxs_lradc_reg_set(lradc,
lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); chan << LRADC_CTRL4_LRADCSELECT_OFFSET(slot),
LRADC_CTRL4);
} }
writel(0xffffffff, lradc->base + LRADC_CH(slot) + STMP_OFFSET_REG_CLR); mxs_lradc_reg_clear(lradc, 0xffffffff, LRADC_CH(slot));
writel(1 << slot, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); mxs_lradc_reg_set(lradc, 1 << slot, LRADC_CTRL0);
delay = jiffies + msecs_to_jiffies(LRADC_TS_SAMPLE_DELAY_MS); delay = jiffies + msecs_to_jiffies(LRADC_TS_SAMPLE_DELAY_MS);
do { do {
...@@ -410,8 +457,7 @@ static int32_t mxs_lradc_ts_sample(struct mxs_lradc *lradc, ...@@ -410,8 +457,7 @@ static int32_t mxs_lradc_ts_sample(struct mxs_lradc *lradc,
break; break;
} while (time_before(jiff, delay)); } while (time_before(jiff, delay));
writel(LRADC_CTRL1_LRADC_IRQ(slot), mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(slot), LRADC_CTRL1);
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
if (time_after_eq(jiff, delay)) if (time_after_eq(jiff, delay))
return -ETIMEDOUT; return -ETIMEDOUT;
...@@ -450,8 +496,8 @@ static void mxs_lradc_ts_work(struct work_struct *ts_work) ...@@ -450,8 +496,8 @@ static void mxs_lradc_ts_work(struct work_struct *ts_work)
while (mxs_lradc_ts_touched(lradc)) { while (mxs_lradc_ts_touched(lradc)) {
/* Disable touch detector so we can sample the touchscreen. */ /* Disable touch detector so we can sample the touchscreen. */
writel(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE, mxs_lradc_reg_clear(lradc, mxs_lradc_touch_detect_bit(lradc),
lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); LRADC_CTRL0);
if (likely(valid)) { if (likely(valid)) {
input_report_abs(lradc->ts_input, ABS_X, val_x); input_report_abs(lradc->ts_input, ABS_X, val_x);
...@@ -485,10 +531,8 @@ static void mxs_lradc_ts_work(struct work_struct *ts_work) ...@@ -485,10 +531,8 @@ static void mxs_lradc_ts_work(struct work_struct *ts_work)
return; return;
/* Restart the touchscreen interrupts. */ /* Restart the touchscreen interrupts. */
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ, mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ, LRADC_CTRL1);
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
} }
static int mxs_lradc_ts_open(struct input_dev *dev) static int mxs_lradc_ts_open(struct input_dev *dev)
...@@ -499,12 +543,11 @@ static int mxs_lradc_ts_open(struct input_dev *dev) ...@@ -499,12 +543,11 @@ static int mxs_lradc_ts_open(struct input_dev *dev)
lradc->stop_touchscreen = false; lradc->stop_touchscreen = false;
/* Enable the touch-detect circuitry. */ /* Enable the touch-detect circuitry. */
writel(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE, mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); LRADC_CTRL0);
/* Enable the touch-detect IRQ. */ /* Enable the touch-detect IRQ. */
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
return 0; return 0;
} }
...@@ -521,12 +564,11 @@ static void mxs_lradc_ts_close(struct input_dev *dev) ...@@ -521,12 +564,11 @@ static void mxs_lradc_ts_close(struct input_dev *dev)
cancel_work_sync(&lradc->ts_work); cancel_work_sync(&lradc->ts_work);
/* Disable touchscreen touch-detect IRQ. */ /* Disable touchscreen touch-detect IRQ. */
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); LRADC_CTRL1);
/* Power-down touchscreen touch-detect circuitry. */ /* Power-down touchscreen touch-detect circuitry. */
writel(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE, mxs_lradc_reg_clear(lradc, mxs_lradc_touch_detect_bit(lradc), LRADC_CTRL0);
lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
} }
static int mxs_lradc_ts_register(struct mxs_lradc *lradc) static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
...@@ -589,7 +631,7 @@ static irqreturn_t mxs_lradc_handle_irq(int irq, void *data) ...@@ -589,7 +631,7 @@ static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
LRADC_CTRL1_TOUCH_DETECT_IRQ_EN | LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
LRADC_CTRL1_TOUCH_DETECT_IRQ; LRADC_CTRL1_TOUCH_DETECT_IRQ;
if (!(reg & LRADC_CTRL1_MX28_LRADC_IRQ_MASK)) if (!(reg & mxs_lradc_irq_mask(lradc)))
return IRQ_NONE; return IRQ_NONE;
/* /*
...@@ -598,8 +640,7 @@ static irqreturn_t mxs_lradc_handle_irq(int irq, void *data) ...@@ -598,8 +640,7 @@ static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
* it ASAP * it ASAP
*/ */
if (reg & LRADC_CTRL1_TOUCH_DETECT_IRQ) { if (reg & LRADC_CTRL1_TOUCH_DETECT_IRQ) {
writel(ts_irq_mask, mxs_lradc_reg_clear(lradc, ts_irq_mask, LRADC_CTRL1);
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
if (!lradc->stop_touchscreen) if (!lradc->stop_touchscreen)
schedule_work(&lradc->ts_work); schedule_work(&lradc->ts_work);
} }
...@@ -609,8 +650,7 @@ static irqreturn_t mxs_lradc_handle_irq(int irq, void *data) ...@@ -609,8 +650,7 @@ static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
complete(&lradc->completion); complete(&lradc->completion);
writel(reg & LRADC_CTRL1_MX28_LRADC_IRQ_MASK, mxs_lradc_reg_clear(lradc, reg & mxs_lradc_irq_mask(lradc), LRADC_CTRL1);
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
...@@ -629,7 +669,7 @@ static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p) ...@@ -629,7 +669,7 @@ static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
lradc->buffer[j] = readl(lradc->base + LRADC_CH(j)); lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
writel(chan_value, lradc->base + LRADC_CH(j)); mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
lradc->buffer[j] &= LRADC_CH_VALUE_MASK; lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP; lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
j++; j++;
...@@ -648,7 +688,7 @@ static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state) ...@@ -648,7 +688,7 @@ static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
struct mxs_lradc *lradc = iio_priv(iio); struct mxs_lradc *lradc = iio_priv(iio);
const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st); mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
return 0; return 0;
} }
...@@ -724,29 +764,26 @@ static int mxs_lradc_buffer_preenable(struct iio_dev *iio) ...@@ -724,29 +764,26 @@ static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
if (ret < 0) if (ret < 0)
goto err_buf; goto err_buf;
writel(LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK, mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); LRADC_CTRL1);
writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs); ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs); ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs); ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
writel(chan_value, lradc->base + LRADC_CH(ofs)); mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
bitmap_set(&enable, ofs, 1); bitmap_set(&enable, ofs, 1);
ofs++; ofs++;
} }
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK, mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); LRADC_DELAY_KICK, LRADC_DELAY(0));
mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
writel(ctrl4_clr, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
writel(ctrl4_set, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); LRADC_DELAY(0));
writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
return 0; return 0;
...@@ -761,12 +798,12 @@ static int mxs_lradc_buffer_postdisable(struct iio_dev *iio) ...@@ -761,12 +798,12 @@ static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
{ {
struct mxs_lradc *lradc = iio_priv(iio); struct mxs_lradc *lradc = iio_priv(iio);
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK, mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); LRADC_DELAY_KICK, LRADC_DELAY(0));
writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
writel(LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK, mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); LRADC_CTRL1);
kfree(lradc->buffer); kfree(lradc->buffer);
mutex_unlock(&lradc->lock); mutex_unlock(&lradc->lock);
...@@ -861,24 +898,24 @@ static int mxs_lradc_hw_init(struct mxs_lradc *lradc) ...@@ -861,24 +898,24 @@ static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
return ret; return ret;
/* Configure DELAY CHANNEL 0 for generic ADC sampling. */ /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
writel(adc_cfg, lradc->base + LRADC_DELAY(0)); mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
/* Disable remaining DELAY CHANNELs */ /* Disable remaining DELAY CHANNELs */
writel(0, lradc->base + LRADC_DELAY(1)); mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
writel(0, lradc->base + LRADC_DELAY(2)); mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
writel(0, lradc->base + LRADC_DELAY(3)); mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
/* Configure the touchscreen type */ /* Configure the touchscreen type */
writel(LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE, mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); LRADC_CTRL0);
if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE) { if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
writel(LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE, mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); LRADC_CTRL0);
} }
/* Start internal temperature sensing. */ /* Start internal temperature sensing. */
writel(0, lradc->base + LRADC_CTRL2); mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
return 0; return 0;
} }
...@@ -887,11 +924,10 @@ static void mxs_lradc_hw_stop(struct mxs_lradc *lradc) ...@@ -887,11 +924,10 @@ static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
{ {
int i; int i;
writel(LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK, mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++) for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
writel(0, lradc->base + LRADC_DELAY(i)); mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
} }
static const struct of_device_id mxs_lradc_dt_ids[] = { static const struct of_device_id mxs_lradc_dt_ids[] = {
......
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