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Kirill Smelkov
linux
Commits
f15bdfe4
Commit
f15bdfe4
authored
Aug 05, 2014
by
Russell King
Browse files
Options
Browse Files
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Plain Diff
Merge branch 'devel-stable' into for-next
Conflicts: arch/arm/kernel/perf_event_cpu.c
parents
c89c3a6a
c70fbb01
Changes
10
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Showing
10 changed files
with
362 additions
and
1107 deletions
+362
-1107
arch/arm/include/asm/memory.h
arch/arm/include/asm/memory.h
+1
-3
arch/arm/include/asm/perf_event.h
arch/arm/include/asm/perf_event.h
+0
-9
arch/arm/include/asm/pmu.h
arch/arm/include/asm/pmu.h
+19
-0
arch/arm/include/asm/uaccess.h
arch/arm/include/asm/uaccess.h
+1
-1
arch/arm/kernel/perf_event.c
arch/arm/kernel/perf_event.c
+11
-2
arch/arm/kernel/perf_event_cpu.c
arch/arm/kernel/perf_event_cpu.c
+10
-3
arch/arm/kernel/perf_event_v6.c
arch/arm/kernel/perf_event_v6.c
+79
-228
arch/arm/kernel/perf_event_v7.c
arch/arm/kernel/perf_event_v7.c
+216
-751
arch/arm/kernel/perf_event_xscale.c
arch/arm/kernel/perf_event_xscale.c
+17
-104
arch/arm/oprofile/common.c
arch/arm/oprofile/common.c
+8
-6
No files found.
arch/arm/include/asm/memory.h
View file @
f15bdfe4
...
...
@@ -91,9 +91,7 @@
* of this define that was meant to.
* Fortunately, there is no reference for this in noMMU mode, for now.
*/
#ifndef TASK_SIZE
#define TASK_SIZE (CONFIG_DRAM_SIZE)
#endif
#define TASK_SIZE UL(0xffffffff)
#ifndef TASK_UNMAPPED_BASE
#define TASK_UNMAPPED_BASE UL(0x00000000)
...
...
arch/arm/include/asm/perf_event.h
View file @
f15bdfe4
...
...
@@ -12,15 +12,6 @@
#ifndef __ARM_PERF_EVENT_H__
#define __ARM_PERF_EVENT_H__
/*
* The ARMv7 CPU PMU supports up to 32 event counters.
*/
#define ARMPMU_MAX_HWEVENTS 32
#define HW_OP_UNSUPPORTED 0xFFFF
#define C(_x) PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED 0xFFFF
#ifdef CONFIG_HW_PERF_EVENTS
struct
pt_regs
;
extern
unsigned
long
perf_instruction_pointer
(
struct
pt_regs
*
regs
);
...
...
arch/arm/include/asm/pmu.h
View file @
f15bdfe4
...
...
@@ -42,6 +42,25 @@ struct arm_pmu_platdata {
#ifdef CONFIG_HW_PERF_EVENTS
/*
* The ARMv7 CPU PMU supports up to 32 event counters.
*/
#define ARMPMU_MAX_HWEVENTS 32
#define HW_OP_UNSUPPORTED 0xFFFF
#define C(_x) PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED 0xFFFF
#define PERF_MAP_ALL_UNSUPPORTED \
[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
[0 ... C(MAX) - 1] = { \
[0 ... C(OP_MAX) - 1] = { \
[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
}, \
}
/* The events for a given PMU register set. */
struct
pmu_hw_events
{
/*
...
...
arch/arm/include/asm/uaccess.h
View file @
f15bdfe4
...
...
@@ -242,7 +242,7 @@ static inline void set_fs(mm_segment_t fs)
#define access_ok(type,addr,size) (__range_ok(addr,size) == 0)
#define user_addr_max() \
(segment_eq(get_fs(),
USER_DS) ? TASK_SIZE : ~0UL
)
(segment_eq(get_fs(),
KERNEL_DS) ? ~0UL : get_fs()
)
/*
* The "__xxx" versions of the user access functions do not verify the
...
...
arch/arm/kernel/perf_event.c
View file @
f15bdfe4
...
...
@@ -560,11 +560,16 @@ user_backtrace(struct frame_tail __user *tail,
struct
perf_callchain_entry
*
entry
)
{
struct
frame_tail
buftail
;
unsigned
long
err
;
/* Also check accessibility of one struct frame_tail beyond */
if
(
!
access_ok
(
VERIFY_READ
,
tail
,
sizeof
(
buftail
)))
return
NULL
;
if
(
__copy_from_user_inatomic
(
&
buftail
,
tail
,
sizeof
(
buftail
)))
pagefault_disable
();
err
=
__copy_from_user_inatomic
(
&
buftail
,
tail
,
sizeof
(
buftail
));
pagefault_enable
();
if
(
err
)
return
NULL
;
perf_callchain_store
(
entry
,
buftail
.
lr
);
...
...
@@ -590,6 +595,10 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
}
perf_callchain_store
(
entry
,
regs
->
ARM_pc
);
if
(
!
current
->
mm
)
return
;
tail
=
(
struct
frame_tail
__user
*
)
regs
->
ARM_fp
-
1
;
while
((
entry
->
nr
<
PERF_MAX_STACK_DEPTH
)
&&
...
...
arch/arm/kernel/perf_event_cpu.c
View file @
f15bdfe4
...
...
@@ -233,14 +233,17 @@ static struct of_device_id cpu_pmu_of_device_ids[] = {
{.
compatible
=
"arm,cortex-a7-pmu"
,
.
data
=
armv7_a7_pmu_init
},
{.
compatible
=
"arm,cortex-a5-pmu"
,
.
data
=
armv7_a5_pmu_init
},
{.
compatible
=
"arm,arm11mpcore-pmu"
,
.
data
=
armv6mpcore_pmu_init
},
{.
compatible
=
"arm,arm1176-pmu"
,
.
data
=
armv6pmu_init
},
{.
compatible
=
"arm,arm1136-pmu"
,
.
data
=
armv6pmu_init
},
{.
compatible
=
"arm,arm1176-pmu"
,
.
data
=
armv6
_1176_
pmu_init
},
{.
compatible
=
"arm,arm1136-pmu"
,
.
data
=
armv6
_1136_
pmu_init
},
{.
compatible
=
"qcom,krait-pmu"
,
.
data
=
krait_pmu_init
},
{},
};
static
struct
platform_device_id
cpu_pmu_plat_device_ids
[]
=
{
{.
name
=
"arm-pmu"
},
{.
name
=
"armv6-pmu"
},
{.
name
=
"armv7-pmu"
},
{.
name
=
"xscale-pmu"
},
{},
};
...
...
@@ -257,9 +260,13 @@ static int probe_current_pmu(struct arm_pmu *pmu)
switch
(
read_cpuid_part
())
{
/* ARM Ltd CPUs. */
case
ARM_CPU_PART_ARM1136
:
ret
=
armv6_1136_pmu_init
(
pmu
);
break
;
case
ARM_CPU_PART_ARM1156
:
ret
=
armv6_1156_pmu_init
(
pmu
);
break
;
case
ARM_CPU_PART_ARM1176
:
ret
=
armv6pmu_init
(
pmu
);
ret
=
armv6
_1176_
pmu_init
(
pmu
);
break
;
case
ARM_CPU_PART_ARM11MPCORE
:
ret
=
armv6mpcore_pmu_init
(
pmu
);
...
...
arch/arm/kernel/perf_event_v6.c
View file @
f15bdfe4
...
...
@@ -65,13 +65,11 @@ enum armv6_counters {
* accesses/misses in hardware.
*/
static
const
unsigned
armv6_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV6_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV6_PERFCTR_INSTR_EXEC
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV6_PERFCTR_BR_EXEC
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV6_PERFCTR_BR_MISPREDICT
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
ARMV6_PERFCTR_IBUF_STALL
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
ARMV6_PERFCTR_LSU_FULL_STALL
,
};
...
...
@@ -79,116 +77,31 @@ static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
static
const
unsigned
armv6_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
/*
* The performance counters don't differentiate between read
* and write accesses/misses so this isn't strictly correct,
* but it's the best we can do. Writes and reads get
* combined.
* The performance counters don't differentiate between read and write
* accesses/misses so this isn't strictly correct, but it's the best we
* can do. Writes and reads get combined.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV6_PERFCTR_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_DCACHE_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV6_PERFCTR_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_DCACHE_MISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_ICACHE_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV6_PERFCTR_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_DCACHE_MISS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV6_PERFCTR_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_DCACHE_MISS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_ICACHE_MISS
,
/*
* The ARM performance counters can count micro DTLB misses,
* micro ITLB misses and main TLB misses. There isn't an event
* for TLB misses, so use the micro misses here and if users
* want the main TLB misses they
can use a raw counter.
* The ARM performance counters can count micro DTLB misses, micro ITLB
* misses and main TLB misses. There isn't an event for TLB misses, so
* use the micro misses here and if users want the main TLB misses they
*
can use a raw counter.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_DTLB_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_DTLB_MISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_ITLB_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_ITLB_MISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_DTLB_MISS
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_DTLB_MISS
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_ITLB_MISS
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV6_PERFCTR_ITLB_MISS
,
};
enum
armv6mpcore_perf_types
{
...
...
@@ -220,13 +133,11 @@ enum armv6mpcore_perf_types {
* accesses/misses in hardware.
*/
static
const
unsigned
armv6mpcore_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV6MPCORE_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV6MPCORE_PERFCTR_INSTR_EXEC
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV6MPCORE_PERFCTR_BR_EXEC
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV6MPCORE_PERFCTR_BR_MISPREDICT
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
ARMV6MPCORE_PERFCTR_IBUF_STALL
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
ARMV6MPCORE_PERFCTR_LSU_FULL_STALL
,
};
...
...
@@ -234,114 +145,26 @@ static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
static
const
unsigned
armv6mpcore_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_DCACHE_RDMISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_DCACHE_WRMISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_ICACHE_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_DCACHE_RDMISS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_DCACHE_WRMISS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_ICACHE_MISS
,
/*
* The ARM performance counters can count micro DTLB misses,
* micro ITLB misses and main TLB misses. There isn't an event
* for TLB misses, so use the micro misses here and if users
* want the main TLB misses they
can use a raw counter.
* The ARM performance counters can count micro DTLB misses, micro ITLB
* misses and main TLB misses. There isn't an event for TLB misses, so
* use the micro misses here and if users want the main TLB misses they
*
can use a raw counter.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_DTLB_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_DTLB_MISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_ITLB_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_ITLB_MISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_DTLB_MISS
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_DTLB_MISS
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_ITLB_MISS
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV6MPCORE_PERFCTR_ITLB_MISS
,
};
static
inline
unsigned
long
...
...
@@ -653,9 +476,8 @@ static int armv6_map_event(struct perf_event *event)
&
armv6_perf_cache_map
,
0xFF
);
}
static
int
armv6pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
static
void
armv6pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
cpu_pmu
->
name
=
"v6"
;
cpu_pmu
->
handle_irq
=
armv6pmu_handle_irq
;
cpu_pmu
->
enable
=
armv6pmu_enable_event
;
cpu_pmu
->
disable
=
armv6pmu_disable_event
;
...
...
@@ -667,7 +489,26 @@ static int armv6pmu_init(struct arm_pmu *cpu_pmu)
cpu_pmu
->
map_event
=
armv6_map_event
;
cpu_pmu
->
num_events
=
3
;
cpu_pmu
->
max_period
=
(
1LLU
<<
32
)
-
1
;
}
static
int
armv6_1136_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv6pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"armv6_1136"
;
return
0
;
}
static
int
armv6_1156_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv6pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"armv6_1156"
;
return
0
;
}
static
int
armv6_1176_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv6pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"armv6_1176"
;
return
0
;
}
...
...
@@ -687,7 +528,7 @@ static int armv6mpcore_map_event(struct perf_event *event)
static
int
armv6mpcore_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
cpu_pmu
->
name
=
"
v6
mpcore"
;
cpu_pmu
->
name
=
"
armv6_11
mpcore"
;
cpu_pmu
->
handle_irq
=
armv6pmu_handle_irq
;
cpu_pmu
->
enable
=
armv6pmu_enable_event
;
cpu_pmu
->
disable
=
armv6mpcore_pmu_disable_event
;
...
...
@@ -703,7 +544,17 @@ static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
return
0
;
}
#else
static
int
armv6pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
static
int
armv6_1136_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
return
-
ENODEV
;
}
static
int
armv6_1156_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
return
-
ENODEV
;
}
static
int
armv6_1176_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
return
-
ENODEV
;
}
...
...
arch/arm/kernel/perf_event_v7.c
View file @
f15bdfe4
...
...
@@ -148,137 +148,62 @@ enum krait_perf_types {
* accesses/misses in hardware.
*/
static
const
unsigned
armv7_a8_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV7_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV7_PERFCTR_INSTR_EXECUTED
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV7_PERFCTR_PC_WRITE
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
ARMV7_A8_PERFCTR_STALL_ISIDE
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
HW_OP_UNSUPPORTED
,
};
static
const
unsigned
armv7_a8_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
/*
* The performance counters don't differentiate between read
* and write accesses/misses so this isn't strictly correct,
* but it's the best we can do. Writes and reads get
* combined.
* The performance counters don't differentiate between read and write
* accesses/misses so this isn't strictly correct, but it's the best we
* can do. Writes and reads get combined.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A8_PERFCTR_L2_CACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A8_PERFCTR_L2_CACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A8_PERFCTR_L2_CACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A8_PERFCTR_L2_CACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
LL
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A8_PERFCTR_L2_CACHE_ACCESS
,
[
C
(
LL
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_A8_PERFCTR_L2_CACHE_REFILL
,
[
C
(
LL
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A8_PERFCTR_L2_CACHE_ACCESS
,
[
C
(
LL
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_A8_PERFCTR_L2_CACHE_REFILL
,
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
};
/*
* Cortex-A9 HW events mapping
*/
static
const
unsigned
armv7_a9_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV7_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV7_A9_PERFCTR_INSTR_CORE_RENAME
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV7_PERFCTR_PC_WRITE
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
ARMV7_A9_PERFCTR_STALL_ICACHE
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
ARMV7_A9_PERFCTR_STALL_DISPATCH
,
};
...
...
@@ -286,238 +211,83 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
static
const
unsigned
armv7_a9_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
/*
* The performance counters don't differentiate between read
* and write accesses/misses so this isn't strictly correct,
* but it's the best we can do. Writes and reads get
* combined.
* The performance counters don't differentiate between read and write
* accesses/misses so this isn't strictly correct, but it's the best we
* can do. Writes and reads get combined.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
};
/*
* Cortex-A5 HW events mapping
*/
static
const
unsigned
armv7_a5_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV7_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV7_PERFCTR_INSTR_EXECUTED
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV7_PERFCTR_PC_WRITE
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
HW_OP_UNSUPPORTED
,
};
static
const
unsigned
armv7_a5_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP
,
},
},
[
C
(
L1I
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1D
)][
C
(
OP_PREFETCH
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL
,
[
C
(
L1D
)][
C
(
OP_PREFETCH
)][
C
(
RESULT_MISS
)]
=
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
/*
* The prefetch counters don't differentiate between the I
* side and the
D side.
* The prefetch counters don't differentiate between the I side and the
*
D side.
*/
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)][
C
(
OP_PREFETCH
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL
,
[
C
(
L1I
)][
C
(
OP_PREFETCH
)][
C
(
RESULT_MISS
)]
=
ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP
,
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
};
/*
* Cortex-A15 HW events mapping
*/
static
const
unsigned
armv7_a15_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV7_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV7_PERFCTR_INSTR_EXECUTED
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
...
...
@@ -525,123 +295,48 @@ static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV7_A15_PERFCTR_PC_WRITE_SPEC
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
ARMV7_PERFCTR_BUS_CYCLES
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
HW_OP_UNSUPPORTED
,
};
static
const
unsigned
armv7_a15_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE
,
/*
* Not all performance counters differentiate between read
* and write accesses/misses so we're not always strictly
* correct, but it's the best we can do. Writes and reads get
* combined in these cases.
* Not all performance counters differentiate between read and write
* accesses/misses so we're not always strictly correct, but it's the
* best we can do. Writes and reads get combined in these cases.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
LL
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ
,
[
C
(
LL
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ
,
[
C
(
LL
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE
,
[
C
(
LL
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE
,
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
};
/*
* Cortex-A7 HW events mapping
*/
static
const
unsigned
armv7_a7_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV7_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV7_PERFCTR_INSTR_EXECUTED
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
...
...
@@ -649,123 +344,48 @@ static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = {
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV7_PERFCTR_PC_WRITE
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
ARMV7_PERFCTR_BUS_CYCLES
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
HW_OP_UNSUPPORTED
,
};
static
const
unsigned
armv7_a7_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
/*
* The performance counters don't differentiate between read
* and write accesses/misses so this isn't strictly correct,
* but it's the best we can do. Writes and reads get
* combined.
* The performance counters don't differentiate between read and write
* accesses/misses so this isn't strictly correct, but it's the best we
* can do. Writes and reads get combined.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L2_CACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L2_CACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L2_CACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L2_CACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
LL
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L2_CACHE_ACCESS
,
[
C
(
LL
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L2_CACHE_REFILL
,
[
C
(
LL
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L2_CACHE_ACCESS
,
[
C
(
LL
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L2_CACHE_REFILL
,
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
};
/*
* Cortex-A12 HW events mapping
*/
static
const
unsigned
armv7_a12_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV7_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV7_PERFCTR_INSTR_EXECUTED
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
...
...
@@ -773,138 +393,60 @@ static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = {
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV7_A12_PERFCTR_PC_WRITE_SPEC
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
ARMV7_PERFCTR_BUS_CYCLES
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
HW_OP_UNSUPPORTED
,
};
static
const
unsigned
armv7_a12_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
/*
* Not all performance counters differentiate between read
* and write accesses/misses so we're not always strictly
* correct, but it's the best we can do. Writes and reads get
* combined in these cases.
* Not all performance counters differentiate between read and write
* accesses/misses so we're not always strictly correct, but it's the
* best we can do. Writes and reads get combined in these cases.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L2_CACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L2_CACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_A12_PERFCTR_PF_TLB_REFILL
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_ICACHE_REFILL
,
[
C
(
LL
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ
,
[
C
(
LL
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L2_CACHE_REFILL
,
[
C
(
LL
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE
,
[
C
(
LL
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L2_CACHE_REFILL
,
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_DTLB_REFILL
,
[
C
(
DTLB
)][
C
(
OP_PREFETCH
)][
C
(
RESULT_MISS
)]
=
ARMV7_A12_PERFCTR_PF_TLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_ITLB_REFILL
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
};
/*
* Krait HW events mapping
*/
static
const
unsigned
krait_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV7_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV7_PERFCTR_INSTR_EXECUTED
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
ARMV7_PERFCTR_PC_WRITE
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
ARMV7_PERFCTR_CLOCK_CYCLES
,
};
static
const
unsigned
krait_perf_map_no_branch
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
ARMV7_PERFCTR_CPU_CYCLES
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
ARMV7_PERFCTR_INSTR_EXECUTED
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
ARMV7_PERFCTR_CLOCK_CYCLES
,
};
...
...
@@ -912,110 +454,31 @@ static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = {
static
const
unsigned
krait_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
/*
* The performance counters don't differentiate between read
* and write accesses/misses so this isn't strictly correct,
* but it's the best we can do. Writes and reads get
* combined.
* The performance counters don't differentiate between read and write
* accesses/misses so this isn't strictly correct, but it's the best we
* can do. Writes and reads get combined.
*/
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
KRAIT_PERFCTR_L1_ICACHE_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_DTLB_ACCESS
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_DTLB_ACCESS
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_ITLB_ACCESS
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_ITLB_ACCESS
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_L1_DCACHE_REFILL
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_ICACHE_ACCESS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
KRAIT_PERFCTR_L1_ICACHE_MISS
,
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_DTLB_ACCESS
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_DTLB_ACCESS
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_ITLB_ACCESS
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
KRAIT_PERFCTR_L1_ITLB_ACCESS
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
ARMV7_PERFCTR_PC_BRANCH_PRED
,
[
C
(
BPU
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
};
/*
...
...
@@ -1545,7 +1008,7 @@ static u32 armv7_read_num_pmnc_events(void)
static
int
armv7_a8_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv7pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"
ARMv7 Cortex-A
8"
;
cpu_pmu
->
name
=
"
armv7_cortex_a
8"
;
cpu_pmu
->
map_event
=
armv7_a8_map_event
;
cpu_pmu
->
num_events
=
armv7_read_num_pmnc_events
();
return
0
;
...
...
@@ -1554,7 +1017,7 @@ static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
static
int
armv7_a9_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv7pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"
ARMv7 Cortex-A
9"
;
cpu_pmu
->
name
=
"
armv7_cortex_a
9"
;
cpu_pmu
->
map_event
=
armv7_a9_map_event
;
cpu_pmu
->
num_events
=
armv7_read_num_pmnc_events
();
return
0
;
...
...
@@ -1563,7 +1026,7 @@ static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
static
int
armv7_a5_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv7pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"
ARMv7 Cortex-A
5"
;
cpu_pmu
->
name
=
"
armv7_cortex_a
5"
;
cpu_pmu
->
map_event
=
armv7_a5_map_event
;
cpu_pmu
->
num_events
=
armv7_read_num_pmnc_events
();
return
0
;
...
...
@@ -1572,7 +1035,7 @@ static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
static
int
armv7_a15_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv7pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"
ARMv7 Cortex-A
15"
;
cpu_pmu
->
name
=
"
armv7_cortex_a
15"
;
cpu_pmu
->
map_event
=
armv7_a15_map_event
;
cpu_pmu
->
num_events
=
armv7_read_num_pmnc_events
();
cpu_pmu
->
set_event_filter
=
armv7pmu_set_event_filter
;
...
...
@@ -1582,7 +1045,7 @@ static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
static
int
armv7_a7_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv7pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"
ARMv7 Cortex-A
7"
;
cpu_pmu
->
name
=
"
armv7_cortex_a
7"
;
cpu_pmu
->
map_event
=
armv7_a7_map_event
;
cpu_pmu
->
num_events
=
armv7_read_num_pmnc_events
();
cpu_pmu
->
set_event_filter
=
armv7pmu_set_event_filter
;
...
...
@@ -1592,7 +1055,7 @@ static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
static
int
armv7_a12_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv7pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"
ARMv7 Cortex-A
12"
;
cpu_pmu
->
name
=
"
armv7_cortex_a
12"
;
cpu_pmu
->
map_event
=
armv7_a12_map_event
;
cpu_pmu
->
num_events
=
armv7_read_num_pmnc_events
();
cpu_pmu
->
set_event_filter
=
armv7pmu_set_event_filter
;
...
...
@@ -1602,7 +1065,7 @@ static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
static
int
armv7_a17_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv7_a12_pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"
ARMv7 Cortex-A
17"
;
cpu_pmu
->
name
=
"
armv7_cortex_a
17"
;
return
0
;
}
...
...
@@ -1823,6 +1286,7 @@ static void krait_pmu_disable_event(struct perf_event *event)
unsigned
long
flags
;
struct
hw_perf_event
*
hwc
=
&
event
->
hw
;
int
idx
=
hwc
->
idx
;
struct
arm_pmu
*
cpu_pmu
=
to_arm_pmu
(
event
->
pmu
);
struct
pmu_hw_events
*
events
=
cpu_pmu
->
get_hw_events
();
/* Disable counter and interrupt */
...
...
@@ -1848,6 +1312,7 @@ static void krait_pmu_enable_event(struct perf_event *event)
unsigned
long
flags
;
struct
hw_perf_event
*
hwc
=
&
event
->
hw
;
int
idx
=
hwc
->
idx
;
struct
arm_pmu
*
cpu_pmu
=
to_arm_pmu
(
event
->
pmu
);
struct
pmu_hw_events
*
events
=
cpu_pmu
->
get_hw_events
();
/*
...
...
@@ -1981,7 +1446,7 @@ static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
static
int
krait_pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
armv7pmu_init
(
cpu_pmu
);
cpu_pmu
->
name
=
"
ARMv7 K
rait"
;
cpu_pmu
->
name
=
"
armv7_k
rait"
;
/* Some early versions of Krait don't support PC write events */
if
(
of_property_read_bool
(
cpu_pmu
->
plat_device
->
dev
.
of_node
,
"qcom,no-pc-write"
))
...
...
arch/arm/kernel/perf_event_xscale.c
View file @
f15bdfe4
...
...
@@ -48,118 +48,31 @@ enum xscale_counters {
};
static
const
unsigned
xscale_perf_map
[
PERF_COUNT_HW_MAX
]
=
{
PERF_MAP_ALL_UNSUPPORTED
,
[
PERF_COUNT_HW_CPU_CYCLES
]
=
XSCALE_PERFCTR_CCNT
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
XSCALE_PERFCTR_INSTRUCTION
,
[
PERF_COUNT_HW_CACHE_REFERENCES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
XSCALE_PERFCTR_BRANCH
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
XSCALE_PERFCTR_BRANCH_MISS
,
[
PERF_COUNT_HW_BUS_CYCLES
]
=
HW_OP_UNSUPPORTED
,
[
PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
]
=
XSCALE_PERFCTR_ICACHE_NO_DELIVER
,
[
PERF_COUNT_HW_STALLED_CYCLES_BACKEND
]
=
HW_OP_UNSUPPORTED
,
};
static
const
unsigned
xscale_perf_cache_map
[
PERF_COUNT_HW_CACHE_MAX
]
[
PERF_COUNT_HW_CACHE_OP_MAX
]
[
PERF_COUNT_HW_CACHE_RESULT_MAX
]
=
{
[
C
(
L1D
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
XSCALE_PERFCTR_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_DCACHE_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
XSCALE_PERFCTR_DCACHE_ACCESS
,
[
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_DCACHE_MISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
L1I
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_ICACHE_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
LL
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
DTLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_DTLB_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_DTLB_MISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
ITLB
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_ITLB_MISS
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_ITLB_MISS
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
BPU
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
[
C
(
NODE
)]
=
{
[
C
(
OP_READ
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_WRITE
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
[
C
(
OP_PREFETCH
)]
=
{
[
C
(
RESULT_ACCESS
)]
=
CACHE_OP_UNSUPPORTED
,
[
C
(
RESULT_MISS
)]
=
CACHE_OP_UNSUPPORTED
,
},
},
PERF_CACHE_MAP_ALL_UNSUPPORTED
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_ACCESS
)]
=
XSCALE_PERFCTR_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_DCACHE_MISS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_ACCESS
)]
=
XSCALE_PERFCTR_DCACHE_ACCESS
,
[
C
(
L1D
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_DCACHE_MISS
,
[
C
(
L1I
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_ICACHE_MISS
,
[
C
(
DTLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_DTLB_MISS
,
[
C
(
DTLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_DTLB_MISS
,
[
C
(
ITLB
)][
C
(
OP_READ
)][
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_ITLB_MISS
,
[
C
(
ITLB
)][
C
(
OP_WRITE
)][
C
(
RESULT_MISS
)]
=
XSCALE_PERFCTR_ITLB_MISS
,
};
#define XSCALE_PMU_ENABLE 0x001
...
...
@@ -442,7 +355,7 @@ static int xscale_map_event(struct perf_event *event)
static
int
xscale1pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
cpu_pmu
->
name
=
"xscale1"
;
cpu_pmu
->
name
=
"
armv5_
xscale1"
;
cpu_pmu
->
handle_irq
=
xscale1pmu_handle_irq
;
cpu_pmu
->
enable
=
xscale1pmu_enable_event
;
cpu_pmu
->
disable
=
xscale1pmu_disable_event
;
...
...
@@ -812,7 +725,7 @@ static inline void xscale2pmu_write_counter(struct perf_event *event, u32 val)
static
int
xscale2pmu_init
(
struct
arm_pmu
*
cpu_pmu
)
{
cpu_pmu
->
name
=
"xscale2"
;
cpu_pmu
->
name
=
"
armv5_
xscale2"
;
cpu_pmu
->
handle_irq
=
xscale2pmu_handle_irq
;
cpu_pmu
->
enable
=
xscale2pmu_enable_event
;
cpu_pmu
->
disable
=
xscale2pmu_disable_event
;
...
...
arch/arm/oprofile/common.c
View file @
f15bdfe4
...
...
@@ -33,12 +33,14 @@ static struct op_perf_name {
char
*
perf_name
;
char
*
op_name
;
}
op_perf_name_map
[]
=
{
{
"xscale1"
,
"arm/xscale1"
},
{
"xscale1"
,
"arm/xscale2"
},
{
"v6"
,
"arm/armv6"
},
{
"v6mpcore"
,
"arm/mpcore"
},
{
"ARMv7 Cortex-A8"
,
"arm/armv7"
},
{
"ARMv7 Cortex-A9"
,
"arm/armv7-ca9"
},
{
"armv5_xscale1"
,
"arm/xscale1"
},
{
"armv5_xscale2"
,
"arm/xscale2"
},
{
"armv6_1136"
,
"arm/armv6"
},
{
"armv6_1156"
,
"arm/armv6"
},
{
"armv6_1176"
,
"arm/armv6"
},
{
"armv6_11mpcore"
,
"arm/mpcore"
},
{
"armv7_cortex_a8"
,
"arm/armv7"
},
{
"armv7_cortex_a9"
,
"arm/armv7-ca9"
},
};
char
*
op_name_from_perf_id
(
void
)
...
...
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