Commit f1d0525e authored by Robert Richter's avatar Robert Richter Committed by Dan Williams

cxl/regs: Remove early capability checks in Component Register setup

When probing the Component Registers in function cxl_probe_regs()
there are also checks for the existence of the HDM and RAS
capabilities. The checks may fail for components that do not implement
the HDM capability causing the Component Registers setup to fail too.

Remove the checks for a generalized use of cxl_probe_regs() and check
them directly before mapping the RAS or HDM capabilities. This allows
it to setup other Component Registers esp. of an RCH Downstream Port,
which will be implemented in a follow-on patch.
Signed-off-by: default avatarRobert Richter <rrichter@amd.com>
Signed-off-by: default avatarTerry Bowman <terry.bowman@amd.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-12-terry.bowman@amd.comSigned-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent d8bffff2
...@@ -369,14 +369,6 @@ static int cxl_probe_regs(struct cxl_register_map *map) ...@@ -369,14 +369,6 @@ static int cxl_probe_regs(struct cxl_register_map *map)
case CXL_REGLOC_RBI_COMPONENT: case CXL_REGLOC_RBI_COMPONENT:
comp_map = &map->component_map; comp_map = &map->component_map;
cxl_probe_component_regs(dev, base, comp_map); cxl_probe_component_regs(dev, base, comp_map);
if (!comp_map->hdm_decoder.valid) {
dev_err(dev, "HDM decoder registers not found\n");
return -ENXIO;
}
if (!comp_map->ras.valid)
dev_dbg(dev, "RAS registers not found\n");
dev_dbg(dev, "Set up component registers\n"); dev_dbg(dev, "Set up component registers\n");
break; break;
case CXL_REGLOC_RBI_MEMDEV: case CXL_REGLOC_RBI_MEMDEV:
......
...@@ -630,6 +630,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) ...@@ -630,6 +630,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
if (rc) if (rc)
dev_warn(&pdev->dev, "No component registers (%d)\n", rc); dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
else if (!map.component_map.ras.valid)
dev_dbg(&pdev->dev, "RAS registers not found\n");
cxlds->component_reg_phys = map.resource; cxlds->component_reg_phys = map.resource;
......
...@@ -102,8 +102,11 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) ...@@ -102,8 +102,11 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
return rc; return rc;
cxlhdm = devm_cxl_setup_hdm(port, &info); cxlhdm = devm_cxl_setup_hdm(port, &info);
if (IS_ERR(cxlhdm)) if (IS_ERR(cxlhdm)) {
if (PTR_ERR(cxlhdm) == -ENODEV)
dev_err(&port->dev, "HDM decoder registers not found\n");
return PTR_ERR(cxlhdm); return PTR_ERR(cxlhdm);
}
/* Cache the data early to ensure is_visible() works */ /* Cache the data early to ensure is_visible() works */
read_cdat_data(port); read_cdat_data(port);
......
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