Commit f1f5e414 authored by Alex Smith's avatar Alex Smith Committed by Ralf Baechle

MIPS: Use Ingenic-specific write combine attribute on all Ingenic platforms

The Ingenic-specific write combining cache attribute was defined based
on CONFIG_MACH_JZ4740 and therefore not used on JZ4780. Change this to
CONFIG_MACH_INGENIC so that it gets used on all Ingenic platforms.
Signed-off-by: default avatarAlex Smith <alex.smith@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10769/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8c172467
...@@ -249,7 +249,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) ...@@ -249,7 +249,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
#elif defined(CONFIG_MACH_JZ4740) #elif defined(CONFIG_MACH_INGENIC)
/* Ingenic uses the WA bit to achieve write-combine memory writes */ /* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
......
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