Commit f294c1f7 authored by Martin Habets's avatar Martin Habets Committed by David S. Miller

sfc: Remove support for siena high priority queue

This also removes TC support code, since that was never supported for EF10.
TC support for EF100 is not handled from efx.c.
Signed-off-by: default avatarMartin Habets <habetsm.xilinx@gmail.com>
Acked-by: default avatarEdward Cree <ecree.xilinx@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e714e5b2
......@@ -605,7 +605,6 @@ static const struct net_device_ops efx_netdev_ops = {
#endif
.ndo_get_phys_port_id = efx_get_phys_port_id,
.ndo_get_phys_port_name = efx_get_phys_port_name,
.ndo_setup_tc = efx_setup_tc,
#ifdef CONFIG_RFS_ACCEL
.ndo_rx_flow_steer = efx_filter_rfs,
#endif
......
......@@ -30,8 +30,6 @@ static inline netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct
tx_queue, skb);
}
void efx_xmit_done_single(struct efx_tx_queue *tx_queue);
int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
void *type_data);
extern unsigned int efx_piobuf_size;
/* RX */
......
......@@ -67,9 +67,7 @@
#define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
#define EFX_TXQ_TYPE_OUTER_CSUM 1 /* Outer checksum offload */
#define EFX_TXQ_TYPE_INNER_CSUM 2 /* Inner checksum offload */
#define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
#define EFX_TXQ_TYPES 8
/* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
#define EFX_TXQ_TYPES 4
#define EFX_MAX_TXQ_PER_CHANNEL 4
#define EFX_MAX_TX_QUEUES (EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS)
......
......@@ -517,13 +517,8 @@ netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
unsigned index, type;
EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
index = skb_get_queue_mapping(skb);
type = efx_tx_csum_type_skb(skb);
if (index >= efx->n_tx_channels) {
index -= efx->n_tx_channels;
type |= EFX_TXQ_TYPE_HIGHPRI;
}
/* PTP "event" packet */
if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
......@@ -603,43 +598,5 @@ void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
/* Must be inverse of queue lookup in efx_hard_start_xmit() */
tx_queue->core_txq =
netdev_get_tx_queue(efx->net_dev,
tx_queue->channel->channel +
((tx_queue->type & EFX_TXQ_TYPE_HIGHPRI) ?
efx->n_tx_channels : 0));
}
int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
void *type_data)
{
struct efx_nic *efx = efx_netdev_priv(net_dev);
struct tc_mqprio_qopt *mqprio = type_data;
unsigned tc, num_tc;
if (type != TC_SETUP_QDISC_MQPRIO)
return -EOPNOTSUPP;
/* Only Siena supported highpri queues */
if (efx_nic_rev(efx) > EFX_REV_SIENA_A0)
return -EOPNOTSUPP;
num_tc = mqprio->num_tc;
if (num_tc > EFX_MAX_TX_TC)
return -EINVAL;
mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
if (num_tc == net_dev->num_tc)
return 0;
for (tc = 0; tc < num_tc; tc++) {
net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
}
net_dev->num_tc = num_tc;
return netif_set_real_num_tx_queues(net_dev,
max_t(int, num_tc, 1) *
efx->n_tx_channels);
tx_queue->channel->channel);
}
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