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Commit f2a89d3b authored by Marc Zyngier's avatar Marc Zyngier Committed by Arnd Bergmann
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arm64: dts: Fix broken architected timer interrupt trigger 

The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: default avatarDuc Dang <dhdang@apm.com>
Acked-by: default avatarCarlo Caione <carlo@endlessm.com>
Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
Acked-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 29b4817d
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Showing with 44 additions and 44 deletions
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View file @ f2a89d3b
...@@ -255,10 +255,10 @@ sysmgr: sysmgr@ffd12000 { ...@@ -255,10 +255,10 @@ sysmgr: sysmgr@ffd12000 {
/* Local timer */ /* Local timer */
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xf01>, interrupts = <1 13 0xf08>,
<1 14 0xf01>, <1 14 0xf08>,
<1 11 0xf01>, <1 11 0xf08>,
<1 10 0xf01>; <1 10 0xf08>;
}; };
timer0: timer0@ffc03000 { timer0: timer0@ffc03000 {
......
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View file @ f2a89d3b
...@@ -102,13 +102,13 @@ psci { ...@@ -102,13 +102,13 @@ psci {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 <GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 <GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 <GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>; (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
}; };
xtal: xtal-clk { xtal: xtal-clk {
......
arch/arm64/boot/dts/apm/apm-storm.dtsi
View file @ f2a89d3b
...@@ -110,10 +110,10 @@ gic: interrupt-controller@78010000 { ...@@ -110,10 +110,10 @@ gic: interrupt-controller@78010000 {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
<1 13 0xff01>, /* Non-secure Phys IRQ */ <1 13 0xff08>, /* Non-secure Phys IRQ */
<1 14 0xff01>, /* Virt IRQ */ <1 14 0xff08>, /* Virt IRQ */
<1 15 0xff01>; /* Hyp IRQ */ <1 15 0xff08>; /* Hyp IRQ */
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };
......
arch/arm64/boot/dts/broadcom/ns2.dtsi
View file @ f2a89d3b
...@@ -88,13 +88,13 @@ psci { ...@@ -88,13 +88,13 @@ psci {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_EDGE_RISING)>, IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_EDGE_RISING)>, IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_EDGE_RISING)>, IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_EDGE_RISING)>; IRQ_TYPE_LEVEL_LOW)>;
}; };
pmu { pmu {
......
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
View file @ f2a89d3b
...@@ -354,10 +354,10 @@ cpu@20f { ...@@ -354,10 +354,10 @@ cpu@20f {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <1 13 4>,
<1 14 0xff01>, <1 14 4>,
<1 11 0xff01>, <1 11 4>,
<1 10 0xff01>; <1 10 4>;
}; };
pmu { pmu {
......
arch/arm64/boot/dts/exynos/exynos7.dtsi
View file @ f2a89d3b
...@@ -473,10 +473,10 @@ hsi2c_11: hsi2c@136a0000 { ...@@ -473,10 +473,10 @@ hsi2c_11: hsi2c@136a0000 {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <1 13 0xff08>,
<1 14 0xff01>, <1 14 0xff08>,
<1 11 0xff01>, <1 11 0xff08>,
<1 10 0xff01>; <1 10 0xff08>;
}; };
pmu_system_controller: system-controller@105c0000 { pmu_system_controller: system-controller@105c0000 {
......
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View file @ f2a89d3b
...@@ -119,10 +119,10 @@ reboot { ...@@ -119,10 +119,10 @@ reboot {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0x1>, /* Physical Secure PPI */ interrupts = <1 13 0xf08>, /* Physical Secure PPI */
<1 14 0x1>, /* Physical Non-Secure PPI */ <1 14 0xf08>, /* Physical Non-Secure PPI */
<1 11 0x1>, /* Virtual PPI */ <1 11 0xf08>, /* Virtual PPI */
<1 10 0x1>; /* Hypervisor PPI */ <1 10 0xf08>; /* Hypervisor PPI */
}; };
pmu { pmu {
......
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file @ f2a89d3b
...@@ -191,10 +191,10 @@ reboot { ...@@ -191,10 +191,10 @@ reboot {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
<1 14 0x8>, /* Physical Non-Secure PPI, active-low */ <1 14 4>, /* Physical Non-Secure PPI, active-low */
<1 11 0x8>, /* Virtual PPI, active-low */ <1 11 4>, /* Virtual PPI, active-low */
<1 10 0x8>; /* Hypervisor PPI, active-low */ <1 10 4>; /* Hypervisor PPI, active-low */
}; };
pmu { pmu {
......
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View file @ f2a89d3b
...@@ -122,10 +122,10 @@ gic_v2m3: v2m@2b0000 { ...@@ -122,10 +122,10 @@ gic_v2m3: v2m@2b0000 {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
odmi: odmi@300000 { odmi: odmi@300000 {
......
arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
View file @ f2a89d3b
...@@ -129,10 +129,10 @@ i2c_clk: i2c_clk { ...@@ -129,10 +129,10 @@ i2c_clk: i2c_clk {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xf01>, interrupts = <1 13 4>,
<1 14 0xf01>, <1 14 4>,
<1 11 0xf01>, <1 11 4>,
<1 10 0xf01>; <1 10 4>;
}; };
soc { soc {
......
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file @ f2a89d3b
...@@ -65,10 +65,10 @@ psci { ...@@ -65,10 +65,10 @@ psci {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <1 13 0xf01>, interrupts = <1 13 0xf08>,
<1 14 0xf01>, <1 14 0xf08>,
<1 11 0xf01>, <1 11 0xf08>,
<1 10 0xf01>; <1 10 0xf08>;
}; };
amba_apu { amba_apu {
......
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