Commit f3261156 authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Reject modeset if the dotclock is too high

Reject the modeset if the requested dotclock exceeds the maximum allowed
by the hardware. So far we've only checked this on gen2/3 while also
handling the double wide vs. single wide pipe selection. Extend the
check to all platforms since we have the max dotclock correctly
populated now across the board.

Testcase: igt/kms_invalid_dotclock
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1464114859-15610-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent bb143165
...@@ -6624,10 +6624,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, ...@@ -6624,10 +6624,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev; struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
int clock_limit = dev_priv->max_dotclk_freq;
/* FIXME should check pixel clock limits on all platforms */
if (INTEL_INFO(dev)->gen < 4) { if (INTEL_INFO(dev)->gen < 4) {
int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
/* /*
* Enable double wide mode when the dot clock * Enable double wide mode when the dot clock
...@@ -6635,9 +6635,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, ...@@ -6635,9 +6635,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
*/ */
if (intel_crtc_supports_double_wide(crtc) && if (intel_crtc_supports_double_wide(crtc) &&
adjusted_mode->crtc_clock > clock_limit) { adjusted_mode->crtc_clock > clock_limit) {
clock_limit *= 2; clock_limit = dev_priv->max_dotclk_freq;
pipe_config->double_wide = true; pipe_config->double_wide = true;
} }
}
if (adjusted_mode->crtc_clock > clock_limit) { if (adjusted_mode->crtc_clock > clock_limit) {
DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
...@@ -6645,7 +6646,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, ...@@ -6645,7 +6646,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
yesno(pipe_config->double_wide)); yesno(pipe_config->double_wide));
return -EINVAL; return -EINVAL;
} }
}
/* /*
* Pipe horizontal size must be even in: * Pipe horizontal size must be even in:
......
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