Commit f36dbfe1 authored by Simon Guo's avatar Simon Guo Committed by Michael Ellerman

selftests/powerpc: Fix build errors in powerpc ptrace selftests

GCC 7 will take "r2" in clobber list as an error and it will get
following build errors for powerpc ptrace selftests even with -fno-pic
option:
  ptrace-tm-vsx.c: In function ‘tm_vsx’:
  ptrace-tm-vsx.c:42:2: error: PIC register clobbered by ‘r2’ in ‘asm’
    asm __volatile__(
    ^~~
  make[1]: *** [ptrace-tm-vsx] Error 1
  ptrace-tm-spd-vsx.c: In function ‘tm_spd_vsx’:
  ptrace-tm-spd-vsx.c:55:2: error: PIC register clobbered by ‘r2’ in ‘asm’
    asm __volatile__(
    ^~~
  make[1]: *** [ptrace-tm-spd-vsx] Error 1
  ptrace-tm-spr.c: In function ‘tm_spr’:
  ptrace-tm-spr.c:46:2: error: PIC register clobbered by ‘r2’ in ‘asm’
    asm __volatile__(
    ^~~

Fix the build error by removing "r2" from the clobber list. None of
these asm blocks actually clobber r2.
Reported-by: default avatarSeth Forshee <seth.forshee@canonical.com>
Signed-off-by: default avatarSimon Guo <wei.guo.simon@gmail.com>
Tested-by: default avatarSeth Forshee <seth.forshee@canonical.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 608c0d88
...@@ -79,8 +79,8 @@ void tm_spd_vsx(void) ...@@ -79,8 +79,8 @@ void tm_spd_vsx(void)
: [res] "=r" (result), [texasr] "=r" (texasr) : [res] "=r" (result), [texasr] "=r" (texasr)
: [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt), : [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt),
[sprn_texasr] "i" (SPRN_TEXASR) [sprn_texasr] "i" (SPRN_TEXASR)
: "memory", "r0", "r1", "r2", "r3", "r4", : "memory", "r0", "r1", "r3", "r4",
"r8", "r9", "r10", "r11" "r7", "r8", "r9", "r10", "r11"
); );
if (result) { if (result) {
......
...@@ -76,8 +76,7 @@ void tm_spr(void) ...@@ -76,8 +76,7 @@ void tm_spr(void)
: [tfhar] "=r" (tfhar), [res] "=r" (result), : [tfhar] "=r" (tfhar), [res] "=r" (result),
[texasr] "=r" (texasr), [cptr1] "=r" (cptr1) [texasr] "=r" (texasr), [cptr1] "=r" (cptr1)
: [sprn_texasr] "i" (SPRN_TEXASR) : [sprn_texasr] "i" (SPRN_TEXASR)
: "memory", "r0", "r1", "r2", "r3", "r4", : "memory", "r0", "r8", "r31"
"r8", "r9", "r10", "r11", "r31"
); );
/* There are 2 32bit instructions before tbegin. */ /* There are 2 32bit instructions before tbegin. */
......
...@@ -67,7 +67,7 @@ void tm_vsx(void) ...@@ -67,7 +67,7 @@ void tm_vsx(void)
: [res] "=r" (result), [texasr] "=r" (texasr) : [res] "=r" (result), [texasr] "=r" (texasr)
: [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt), : [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt),
[sprn_texasr] "i" (SPRN_TEXASR), [cptr1] "r" (&cptr[1]) [sprn_texasr] "i" (SPRN_TEXASR), [cptr1] "r" (&cptr[1])
: "memory", "r0", "r1", "r2", "r3", "r4", : "memory", "r0", "r1", "r3", "r4",
"r7", "r8", "r9", "r10", "r11" "r7", "r8", "r9", "r10", "r11"
); );
......
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