Commit f3dfcd25 authored by Raghavendra Rao Ananta's avatar Raghavendra Rao Ananta Committed by Will Deacon

arm64/sysreg: Correct the values for GICv4.1

Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
Hence, correct them to reflect ARM ARM.
Signed-off-by: default avatarRaghavendra Rao Ananta <rananta@google.com>
Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Reviewed-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240718215532.616447-1-rananta@google.comSigned-off-by: default avatarWill Deacon <will@kernel.org>
parent 48f64305
...@@ -149,7 +149,7 @@ Res0 63:32 ...@@ -149,7 +149,7 @@ Res0 63:32
UnsignedEnum 31:28 GIC UnsignedEnum 31:28 GIC
0b0000 NI 0b0000 NI
0b0001 GICv3 0b0001 GICv3
0b0010 GICv4p1 0b0011 GICv4p1
EndEnum EndEnum
UnsignedEnum 27:24 Virt_frac UnsignedEnum 27:24 Virt_frac
0b0000 NI 0b0000 NI
...@@ -903,7 +903,7 @@ EndEnum ...@@ -903,7 +903,7 @@ EndEnum
UnsignedEnum 27:24 GIC UnsignedEnum 27:24 GIC
0b0000 NI 0b0000 NI
0b0001 IMP 0b0001 IMP
0b0010 V4P1 0b0011 V4P1
EndEnum EndEnum
SignedEnum 23:20 AdvSIMD SignedEnum 23:20 AdvSIMD
0b0000 IMP 0b0000 IMP
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment