Commit f46a93b8 authored by Kuninori Morimoto's avatar Kuninori Morimoto Committed by Mark Brown

ASoC: rsnd: ssi: 24bit data needs right-aligned settings

Data left/right aligned is controlled by PDTA bit on SSICR.
But default is left-aligned. Thus 24bit sound will be very small sound
without this patch.
Signed-off-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 85d4a621
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
#define SCKP (1 << 13) /* Serial Bit Clock Polarity */ #define SCKP (1 << 13) /* Serial Bit Clock Polarity */
#define SWSP (1 << 12) /* Serial WS Polarity */ #define SWSP (1 << 12) /* Serial WS Polarity */
#define SDTA (1 << 10) /* Serial Data Alignment */ #define SDTA (1 << 10) /* Serial Data Alignment */
#define PDTA (1 << 9) /* Parallel Data Alignment */
#define DEL (1 << 8) /* Serial Data Delay */ #define DEL (1 << 8) /* Serial Data Delay */
#define CKDV(v) (v << 4) /* Serial Clock Division Ratio */ #define CKDV(v) (v << 4) /* Serial Clock Division Ratio */
#define TRMD (1 << 1) /* Transmit/Receive Mode Select */ #define TRMD (1 << 1) /* Transmit/Receive Mode Select */
...@@ -274,7 +275,7 @@ static int rsnd_ssi_init(struct rsnd_mod *mod, ...@@ -274,7 +275,7 @@ static int rsnd_ssi_init(struct rsnd_mod *mod,
if (rsnd_ssi_is_parent(mod, io)) if (rsnd_ssi_is_parent(mod, io))
return 0; return 0;
cr = FORCE; cr = FORCE | PDTA;
/* /*
* always use 32bit system word for easy clock calculation. * always use 32bit system word for easy clock calculation.
......
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