Commit f4f9f6bf authored by Frank Li's avatar Frank Li Committed by Shawn Guo

arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3

Enable uart2 and uart3 for imx8qxp-mek board.
Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e0d5a28b
...@@ -187,6 +187,18 @@ &lpuart0 { ...@@ -187,6 +187,18 @@ &lpuart0 {
status = "okay"; status = "okay";
}; };
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
&mu_m0 { &mu_m0 {
status = "okay"; status = "okay";
}; };
...@@ -340,6 +352,20 @@ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 ...@@ -340,6 +352,20 @@ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
>; >;
}; };
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
>;
};
pinctrl_typec: typecgrp { pinctrl_typec: typecgrp {
fsl,pins = < fsl,pins = <
IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
......
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