Commit f547b3de authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Linus Walleij

pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base

The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not worked around when
developing the driver, which makes IRQ not working.

Fix the IRQ bank base.

Fixes: 56d9e4a7 ("pinctrl: sunxi: add driver for V3s SoC")
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 3f713b7c
...@@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { ...@@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins, .pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins), .npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2, .irq_banks = 2,
.irq_bank_base = 1,
.irq_read_needs_mux = true .irq_read_needs_mux = true
}; };
......
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