Commit f60a2abf authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The diff is dominated by the Allwinner A10/A20 SoCs getting converted
  to the sunxi-ng framework. Otherwise, the heavy hitters are various
  drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are
  some other new clk drivers in here too but overall this is just a
  bunch of clk drivers for various different pieces of hardware and a
  collection of non-critical fixes for clk drivers.

  New Drivers:
   - Allwinner R40 SoCs
   - Renesas R-Car Gen3 USB 2.0 clock selector PHY
   - Atmel AT91 audio PLL
   - Uniphier PXs3 SoCs
   - ARC HSDK Board PLLs
   - AXS10X Board PLLs
   - STMicroelectronics STM32H743 SoCs

  Removed Drivers:
   - Non-compiling mb86s7x support

  Updates:
   - Allwinner A10/A20 SoCs converted to sunxi-ng framework
   - Allwinner H3 CPU clk fixes
   - Renesas R-Car D3 SoC
   - Renesas V2H and M3-W modules
   - Samsung Exynos5420/5422/5800 audio fixes
   - Rockchip fractional clk approximation fixes
   - Rockchip rk3126 SoC support within the rk3128 driver
   - Amlogic gxbb CEC32 and sd_emmc clks
   - Amlogic meson8b reset controller support
   - IDT VersaClock 5P49V5925/5P49V6901 support
   - Qualcomm MSM8996 SMMU clks
   - Various 'const' applications for struct clk_ops
   - si5351 PLL reset bugfix
   - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
   - Assorted Tegra clk driver fixes"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits)
  clk: si5351: fix PLL reset
  ASoC: atmel-classd: remove aclk clock
  ASoC: atmel-classd: remove aclk clock from DT binding
  clk: at91: clk-generated: make gclk determine audio_pll rate
  clk: at91: clk-generated: create function to find best_diff
  clk: at91: add audio pll clock drivers
  dt-bindings: clk: at91: add audio plls to the compatible list
  clk: at91: clk-generated: remove useless divisor loop
  clk: mb86s7x: Drop non-building driver
  clk: ti: check for null return in strrchr to avoid null dereferencing
  clk: Don't write error code into divider register
  clk: uniphier: add video input subsystem clock
  clk: uniphier: add audio system clock
  clk: stm32h7: Add stm32h743 clock driver
  clk: gate: expose clk_gate_ops::is_enabled
  clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
  clk: uniphier: add PXs3 clock data
  clk: hi6220: change watchdog clock source
  clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
  clk: cs2000: Add cs2000_set_saved_rate
  ...
parents 561a8eb3 73c950da
......@@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
Required Properties:
- compatible: should be "amlogic,gxbb-aoclkc"
- reg: physical base address of the clock controller and length of memory
mapped region.
- compatible: value should be different for each SoC family as :
- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
followed by the common "amlogic,meson-gx-aoclkc"
- #clock-cells: should be 1.
......@@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.
Parent node should have the following properties :
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
- reg: base address and size of the AO system control register space.
Example: AO Clock controller node:
clkc_AO: clock-controller@040 {
compatible = "amlogic,gxbb-aoclkc";
reg = <0x0 0x040 0x0 0x4>;
ao_sysctrl: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
reg = <0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
};
};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:
......
......@@ -81,6 +81,16 @@ Required properties:
"atmel,sama5d2-clk-generated":
at91 generated clock
"atmel,sama5d2-clk-audio-pll-frac":
at91 audio fractional pll
"atmel,sama5d2-clk-audio-pll-pad":
at91 audio pll CLK_AUDIO output pin
"atmel,sama5d2-clk-audio-pll-pmc"
at91 audio pll output on AUDIOPLLCLK that feeds the PMC
and can be used by peripheral clock or generic clock
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
......
Binding for IDT VersaClock5 programmable i2c clock generator.
Binding for IDT VersaClock 5,6 programmable i2c clock generators.
The IDT VersaClock5 are programmable i2c clock generators providing
from 3 to 12 output clocks.
The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
generators providing from 3 to 12 output clocks.
==I2C device node==
Required properties:
- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
"idt,5p49v5935".
- compatible: shall be one of
"idt,5p49v5923"
"idt,5p49v5925"
"idt,5p49v5933"
"idt,5p49v5935"
"idt,5p49v6901"
- reg: i2c device address, shall be 0x68 or 0x6a.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock handles,
- 5p49v5923: (required) either or both of XTAL or CLKIN
- 5p49v5923 and
5p49v5925 and
5p49v6901: (required) either or both of XTAL or CLKIN
reference clock.
- 5p49v5933 and
- 5p49v5935: (optional) property not present (internal
Xtal used) or CLKIN reference
clock.
- clock-names: from common clock binding; clock input names, can be
- 5p49v5923: (required) either or both of "xin", "clkin".
- 5p49v5923 and
5p49v5925 and
5p49v6901: (required) either or both of "xin", "clkin".
- 5p49v5933 and
- 5p49v5935: (optional) property not present or "clkin".
......@@ -37,6 +45,7 @@ clock specifier, the following mapping applies:
1 -- OUT1
2 -- OUT4
5P49V5925 and
5P49V5935:
0 -- OUT0_SEL_I2CB
1 -- OUT1
......@@ -44,6 +53,13 @@ clock specifier, the following mapping applies:
3 -- OUT3
4 -- OUT4
5P49V6901:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
3 -- OUT3
4 -- OUT4
==Example==
/* 25MHz reference crystal */
......
......@@ -22,6 +22,7 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
block
......@@ -30,7 +31,7 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
r8a7795, r8a7796)
r8a7795, r8a7796, r8a77995)
- "extalr" (r8a7795, r8a7796)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
......
* Renesas R-Car USB 2.0 clock selector
This file provides information on what the device node for the R-Car USB 2.0
clock selector.
If you connect an external clock to the USB_EXTAL pin only, you should set
the clock rate to "usb_extal" node only.
If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
is not needed because this is default setting. (Of course, you can set the
clock rates to both "usb_extal" and "usb_xtal" nodes.
Case 1: An external clock connects to R-Car SoC
+----------+ +--- R-Car ---------------------+
|External |---|USB_EXTAL ---> all usb channels|
|clock | |USB_XTAL |
+----------+ +-------------------------------+
In this case, we need this driver with "usb_extal" clock.
Case 2: An oscillator connects to R-Car SoC
+----------+ +--- R-Car ---------------------+
|Oscillator|---|USB_EXTAL -+-> all usb channels|
| |---|USB_XTAL --+ |
+----------+ +-------------------------------+
In this case, we don't need this selector.
Required properties:
- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
an R8A7795 SoC.
"renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
an R8A7796 SoC.
"renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
compatible device.
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first
followed by the generic version.
- reg: offset and length of the USB 2.0 clock selector register block.
- clocks: A list of phandles and specifier pairs.
- clock-names: Name of the clocks.
- The functional clock must be "ehci_ohci"
- The USB_EXTAL clock pin must be "usb_extal"
- The USB_XTAL clock pin must be "usb_xtal"
- #clock-cells: Must be 0
Example (R-Car H3):
usb2_clksel: clock-controller@e6590630 {
compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
"renesas,rcar-gen3-usb2-clock-sel";
reg = <0 0xe6590630 0 0x02>;
clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
#clock-cells = <0>;
};
* Rockchip RK3128 Clock and Reset Unit
* Rockchip RK3126/RK3128 Clock and Reset Unit
The RK3128 clock controller generates and supplies clock to various
The RK3126/RK3128 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: should be "rockchip,rk3128-cru"
- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
"rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
"rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
......
Binding for the HSDK Generic PLL clock
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: should be "snps,hsdk-<name>-pll-clock"
"snps,hsdk-core-pll-clock"
"snps,hsdk-gp-pll-clock"
"snps,hsdk-hdmi-pll-clock"
- reg : should contain base register location and length.
- clocks: shall be the input parent clock phandle for the PLL.
- #clock-cells: from common clock binding; Should always be set to 0.
Example:
input_clk: input-clk {
clock-frequency = <33333333>;
compatible = "fixed-clock";
#clock-cells = <0>;
};
cpu_clk: cpu-clk@0 {
compatible = "snps,hsdk-core-pll-clock";
reg = <0x00 0x10>;
#clock-cells = <0>;
clocks = <&input_clk>;
};
Binding for the AXS10X Generic PLL clock
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: should be "snps,axs10x-<name>-pll-clock"
"snps,axs10x-arc-pll-clock"
"snps,axs10x-pgu-pll-clock"
- reg: should always contain 2 pairs address - length: first for PLL config
registers and second for corresponding LOCK CGU register.
- clocks: shall be the input parent clock phandle for the PLL.
- #clock-cells: from common clock binding; Should always be set to 0.
Example:
input-clk: input-clk {
clock-frequency = <33333333>;
compatible = "fixed-clock";
#clock-cells = <0>;
};
core-clk: core-clk@80 {
compatible = "snps,axs10x-arc-pll-clock";
reg = <0x80 0x10>, <0x100 0x10>;
#clock-cells = <0>;
clocks = <&input-clk>;
};
STMicroelectronics STM32H7 Reset and Clock Controller
=====================================================
The RCC IP is both a reset and a clock controller.
Please refer to clock-bindings.txt for common clock controller binding usage.
Please also refer to reset.txt for common reset controller binding usage.
Required properties:
- compatible: Should be:
"st,stm32h743-rcc"
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
- #clock-cells : from common clock binding; shall be set to 1
- clocks: External oscillator clock phandle
- high speed external clock signal (HSE)
- low speed external clock signal (LSE)
- external I2S clock (I2S_CKIN)
Optional properties:
- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
write protection (RTC clock).
Example:
rcc: reset-clock-controller@58024400 {
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
reg = <0x58024400 0x400>;
#reset-cells = <1>;
#clock-cells = <2>;
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;
};
The peripheral clock consumer should specify the desired clock by
having the clock ID in its "clocks" phandle cell.
Example:
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&rcc TIM5_CK>;
};
Specifying softreset control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the reset device node and an index specifying
which channel to use.
The index is the bit number within the RCC registers bank, starting from RCC
base address.
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register.
For example, for CRC reset:
crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
Example:
timer2 {
resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
};
......@@ -3,18 +3,24 @@ Allwinner Clock Control Unit Binding
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun4i-a10-ccu"
- "allwinner,sun5i-a10s-ccu"
- "allwinner,sun5i-a13-ccu"
- "allwinner,sun6i-a31-ccu"
- "allwinner,sun7i-a20-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-a83t-ccu"
- "allwinner,sun8i-a83t-r-ccu"
- "allwinner,sun8i-h3-ccu"
- "allwinner,sun8i-h3-r-ccu"
+ - "allwinner,sun8i-r40-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
......
......@@ -6,7 +6,6 @@ System clock
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-sld3-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-clock" - for LD4 SoC.
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
......@@ -14,6 +13,7 @@ Required properties:
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-clock" - for LD11 SoC.
"socionext,uniphier-ld20-clock" - for LD20 SoC.
"socionext,uniphier-pxs3-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
......@@ -48,7 +48,6 @@ Media I/O (MIO) clock, SD clock
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
......@@ -56,6 +55,7 @@ Required properties:
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
"socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
......@@ -82,11 +82,9 @@ Provided clocks:
8: USB2 ch0 host
9: USB2 ch1 host
10: USB2 ch2 host
11: USB2 ch3 host
12: USB2 ch0 PHY
13: USB2 ch1 PHY
14: USB2 ch2 PHY
15: USB2 ch3 PHY
Peripheral clock
......@@ -94,7 +92,6 @@ Peripheral clock
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
......@@ -102,6 +99,7 @@ Required properties:
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
"socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
......
......@@ -13,13 +13,11 @@ Required properties:
Must be "tx".
- clock-names
Tuple listing input clock names.
Required elements: "pclk", "gclk" and "aclk".
Required elements: "pclk" and "gclk".
- clocks
Please refer to clock-bindings.txt.
- assigned-clocks
Should be <&classd_gclk>.
- assigned-clock-parents
Should be <&audio_pll_pmc>.
Optional properties:
- pinctrl-names, pinctrl-0
......@@ -45,10 +43,9 @@ classd: classd@fc048000 {
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(47))>;
dma-names = "tx";
clocks = <&classd_clk>, <&classd_gclk>, <&audio_pll_pmc>;
clock-names = "pclk", "gclk", "aclk";
clocks = <&classd_clk>, <&classd_gclk>;
clock-names = "pclk", "gclk";
assigned-clocks = <&classd_gclk>;
assigned-clock-parents = <&audio_pll_pmc>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_classd_default>;
......
......@@ -12842,6 +12842,18 @@ F: drivers/clocksource/arc_timer.c
F: drivers/tty/serial/arc_uart.c
T: git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git
SYNOPSYS ARC HSDK SDP pll clock driver
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
S: Supported
F: drivers/clk/clk-hsdk-pll.c
F: Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
SYNOPSYS ARC SDP clock driver
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
S: Supported
F: drivers/clk/axs10x/*
F: Documentation/devicetree/bindings/clock/snps,pll-clock.txt
SYNOPSYS ARC SDP platform support
M: Alexey Brodkin <abrodkin@synopsys.com>
S: Supported
......
......@@ -26,6 +26,7 @@ config SOC_SAMA5D2
select HAVE_AT91_USB_CLK
select HAVE_AT91_H32MX
select HAVE_AT91_GENERATED_CLK
select HAVE_AT91_AUDIO_PLL
select PINCTRL_AT91PIO4
help
Select this if ou are using one of Atmel's SAMA5D2 family SoC.
......@@ -125,6 +126,9 @@ config HAVE_AT91_H32MX
config HAVE_AT91_GENERATED_CLK
bool
config HAVE_AT91_AUDIO_PLL
bool
config SOC_SAM_V4_V5
bool
......
......@@ -31,6 +31,13 @@ config COMMON_CLK_WM831X
source "drivers/clk/versatile/Kconfig"
config CLK_HSDK
bool "PLL Driver for HSDK platform"
depends on OF || COMPILE_TEST
---help---
This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
control.
config COMMON_CLK_MAX77686
tristate "Clock driver for Maxim 77620/77686/77802 MFD"
depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
......@@ -39,10 +46,10 @@ config COMMON_CLK_MAX77686
clock.
config COMMON_CLK_RK808
tristate "Clock driver for RK808/RK818"
tristate "Clock driver for RK805/RK808/RK818"
depends on MFD_RK808
---help---
This driver supports RK808 and RK818 crystal oscillator clock. These
This driver supports RK805, RK808 and RK818 crystal oscillator clock. These
multi-function devices have two fixed-rate oscillators,
clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
by control register.
......@@ -210,14 +217,14 @@ config COMMON_CLK_OXNAS
Support for the OXNAS SoC Family clocks.
config COMMON_CLK_VC5
tristate "Clock driver for IDT VersaClock5 devices"
tristate "Clock driver for IDT VersaClock 5,6 devices"
depends on I2C
depends on OF
select REGMAP_I2C
help
---help---
This driver supports the IDT VersaClock5 programmable clock
generator.
This driver supports the IDT VersaClock 5 and VersaClock 6
programmable clock generators.
source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig"
......
......@@ -27,8 +27,8 @@ obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
......@@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o
obj-$(CONFIG_ARCH_STM32) += clk-stm32h7.o
obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_ARCH_U300) += clk-u300.o
......
......@@ -6,6 +6,7 @@ obj-y += pmc.o sckc.o
obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o clk-programmable.o
obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
......
This diff is collapsed.
......@@ -26,6 +26,13 @@
#define GENERATED_SOURCE_MAX 6
#define GENERATED_MAX_DIV 255
#define GCK_ID_SSC0 43
#define GCK_ID_SSC1 44
#define GCK_ID_I2S0 54
#define GCK_ID_I2S1 55
#define GCK_ID_CLASSD 59
#define GCK_INDEX_DT_AUDIO_PLL 5
struct clk_generated {
struct clk_hw hw;
struct regmap *regmap;
......@@ -34,6 +41,7 @@ struct clk_generated {
u32 id;
u32 gckdiv;
u8 parent_id;
bool audio_pll_allowed;
};
#define to_clk_generated(hw) \
......@@ -99,21 +107,41 @@ clk_generated_recalc_rate(struct clk_hw *hw,
return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
}
static void clk_generated_best_diff(struct clk_rate_request *req,
struct clk_hw *parent,
unsigned long parent_rate, u32 div,
int *best_diff, long *best_rate)
{
unsigned long tmp_rate;
int tmp_diff;
if (!div)
tmp_rate = parent_rate;
else
tmp_rate = parent_rate / div;
tmp_diff = abs(req->rate - tmp_rate);
if (*best_diff < 0 || *best_diff > tmp_diff) {
*best_rate = tmp_rate;
*best_diff = tmp_diff;
req->best_parent_rate = parent_rate;
req->best_parent_hw = parent;
}
}
static int clk_generated_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_generated *gck = to_clk_generated(hw);
struct clk_hw *parent = NULL;
struct clk_rate_request req_parent = *req;
long best_rate = -EINVAL;
unsigned long tmp_rate, min_rate;
unsigned long min_rate, parent_rate;
int best_diff = -1;
int tmp_diff;
int i;
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
u32 div;
unsigned long parent_rate;
for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
parent = clk_hw_get_parent_by_index(hw, i);
if (!parent)
continue;
......@@ -124,25 +152,43 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
(gck->range.max && min_rate > gck->range.max))
continue;
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
tmp_diff = abs(req->rate - tmp_rate);
div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
if (best_diff < 0 || best_diff > tmp_diff) {
best_rate = tmp_rate;
best_diff = tmp_diff;
req->best_parent_rate = parent_rate;
req->best_parent_hw = parent;
}
clk_generated_best_diff(req, parent, parent_rate, div,
&best_diff, &best_rate);
if (!best_diff || tmp_rate < req->rate)
if (!best_diff)
break;
}
/*
* The audio_pll rate can be modified, unlike the five others clocks
* that should never be altered.
* The audio_pll can technically be used by multiple consumers. However,
* with the rate locking, the first consumer to enable to clock will be
* the one definitely setting the rate of the clock.
* Since audio IPs are most likely to request the same rate, we enforce
* that the only clks able to modify gck rate are those of audio IPs.
*/
if (!gck->audio_pll_allowed)
goto end;
parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
if (!parent)
goto end;
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
req_parent.rate = req->rate * div;
__clk_determine_rate(parent, &req_parent);
clk_generated_best_diff(req, parent, req_parent.rate, div,
&best_diff, &best_rate);
if (!best_diff)
break;
}
end:
pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
__func__, best_rate,
__clk_get_name((req->best_parent_hw)->clk),
......@@ -252,7 +298,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
init.ops = &generated_ops;
init.parent_names = parent_names;
init.num_parents = num_parents;
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
CLK_SET_RATE_PARENT;
gck->id = id;
gck->hw.init = &init;
......@@ -284,6 +331,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
struct device_node *gcknp;
struct clk_range range = CLK_RANGE(0, 0);
struct regmap *regmap;
struct clk_generated *gck;
num_parents = of_clk_get_parent_count(np);
if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
......@@ -315,6 +363,21 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
parent_names, num_parents,
id, &range);
gck = to_clk_generated(hw);
if (of_device_is_compatible(np,
"atmel,sama5d2-clk-generated")) {
if (gck->id == GCK_ID_SSC0 || gck->id == GCK_ID_SSC1 ||
gck->id == GCK_ID_I2S0 || gck->id == GCK_ID_I2S1 ||
gck->id == GCK_ID_CLASSD)
gck->audio_pll_allowed = true;
else
gck->audio_pll_allowed = false;
} else {
gck->audio_pll_allowed = false;
}
if (IS_ERR(hw))
continue;
......
obj-y += i2s_pll_clock.o
obj-y += pll_clock.o
/*
* Synopsys AXS10X SDP Generic PLL clock driver
*
* Copyright (C) 2017 Synopsys
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/of.h>
/* PLL registers addresses */
#define PLL_REG_IDIV 0x0
#define PLL_REG_FBDIV 0x4
#define PLL_REG_ODIV 0x8
/*
* Bit fields of the PLL IDIV/FBDIV/ODIV registers:
* ________________________________________________________________________
* |31 15| 14 | 13 | 12 |11 6|5 0|
* |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
* |____________________|__________|________|______|____________|___________|
*
* Following macros determine the way of access to these registers
* They should be set up only using the macros.
* reg should be an u32 variable.
*/
#define PLL_REG_GET_LOW(reg) \
(((reg) & (0x3F << 0)) >> 0)
#define PLL_REG_GET_HIGH(reg) \
(((reg) & (0x3F << 6)) >> 6)
#define PLL_REG_GET_EDGE(reg) \
(((reg) & (BIT(12))) ? 1 : 0)
#define PLL_REG_GET_BYPASS(reg) \
(((reg) & (BIT(13))) ? 1 : 0)
#define PLL_REG_GET_NOUPD(reg) \
(((reg) & (BIT(14))) ? 1 : 0)
#define PLL_REG_GET_PAD(reg) \
(((reg) & (0x1FFFF << 15)) >> 15)
#define PLL_REG_SET_LOW(reg, value) \
{ reg |= (((value) & 0x3F) << 0); }
#define PLL_REG_SET_HIGH(reg, value) \
{ reg |= (((value) & 0x3F) << 6); }
#define PLL_REG_SET_EDGE(reg, value) \
{ reg |= (((value) & 0x01) << 12); }
#define PLL_REG_SET_BYPASS(reg, value) \
{ reg |= (((value) & 0x01) << 13); }
#define PLL_REG_SET_NOUPD(reg, value) \
{ reg |= (((value) & 0x01) << 14); }
#define PLL_REG_SET_PAD(reg, value) \
{ reg |= (((value) & 0x1FFFF) << 15); }
#define PLL_LOCK BIT(0)
#define PLL_ERROR BIT(1)
#define PLL_MAX_LOCK_TIME 100 /* 100 us */
struct axs10x_pll_cfg {
u32 rate;
u32 idiv;
u32 fbdiv;
u32 odiv;
};
static const struct axs10x_pll_cfg arc_pll_cfg[] = {
{ 33333333, 1, 1, 1 },
{ 50000000, 1, 30, 20 },
{ 75000000, 2, 45, 10 },
{ 90000000, 2, 54, 10 },
{ 100000000, 1, 30, 10 },
{ 125000000, 2, 45, 6 },
{}
};
static const struct axs10x_pll_cfg pgu_pll_cfg[] = {
{ 25200000, 1, 84, 90 },
{ 50000000, 1, 100, 54 },
{ 74250000, 1, 44, 16 },
{}
};
struct axs10x_pll_clk {
struct clk_hw hw;
void __iomem *base;
void __iomem *lock;
const struct axs10x_pll_cfg *pll_cfg;
struct device *dev;
};
static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
u32 val)
{
iowrite32(val, clk->base + reg);
}
static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
{
return ioread32(clk->base + reg);
}
static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)
{
return container_of(hw, struct axs10x_pll_clk, hw);
}
static inline u32 axs10x_div_get_value(u32 reg)
{
if (PLL_REG_GET_BYPASS(reg))
return 1;
return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
}
static inline u32 axs10x_encode_div(unsigned int id, int upd)
{
u32 div = 0;
PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);
PLL_REG_SET_HIGH(div, id >> 1);
PLL_REG_SET_EDGE(div, id % 2);
PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
return div;
}
static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
u64 rate;
u32 idiv, fbdiv, odiv;
struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));
fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));
rate = (u64)parent_rate * fbdiv;
do_div(rate, idiv * odiv);
return rate;
}
static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
int i;
long best_rate;
struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
if (pll_cfg[0].rate == 0)
return -EINVAL;
best_rate = pll_cfg[0].rate;
for (i = 1; pll_cfg[i].rate != 0; i++) {
if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
best_rate = pll_cfg[i].rate;
}
return best_rate;
}
static int axs10x_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
int i;
struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
for (i = 0; pll_cfg[i].rate != 0; i++) {
if (pll_cfg[i].rate == rate) {
axs10x_pll_write(clk, PLL_REG_IDIV,
axs10x_encode_div(pll_cfg[i].idiv, 0));
axs10x_pll_write(clk, PLL_REG_FBDIV,
axs10x_encode_div(pll_cfg[i].fbdiv, 0));
axs10x_pll_write(clk, PLL_REG_ODIV,
axs10x_encode_div(pll_cfg[i].odiv, 1));
/*
* Wait until CGU relocks and check error status.
* If after timeout CGU is unlocked yet return error
*/
udelay(PLL_MAX_LOCK_TIME);
if (!(ioread32(clk->lock) & PLL_LOCK))
return -ETIMEDOUT;
if (ioread32(clk->lock) & PLL_ERROR)
return -EINVAL;
return 0;
}
}
dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
parent_rate);
return -EINVAL;
}
static const struct clk_ops axs10x_pll_ops = {
.recalc_rate = axs10x_pll_recalc_rate,
.round_rate = axs10x_pll_round_rate,
.set_rate = axs10x_pll_set_rate,
};
static int axs10x_pll_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const char *parent_name;
struct axs10x_pll_clk *pll_clk;
struct resource *mem;
struct clk_init_data init = { };
int ret;
pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
if (!pll_clk)
return -ENOMEM;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pll_clk->base = devm_ioremap_resource(dev, mem);
if (IS_ERR(pll_clk->base))
return PTR_ERR(pll_clk->base);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
pll_clk->lock = devm_ioremap_resource(dev, mem);
if (IS_ERR(pll_clk->lock))
return PTR_ERR(pll_clk->lock);
init.name = dev->of_node->name;
init.ops = &axs10x_pll_ops;
parent_name = of_clk_get_parent_name(dev->of_node, 0);
init.parent_names = &parent_name;
init.num_parents = 1;
pll_clk->hw.init = &init;
pll_clk->dev = dev;
pll_clk->pll_cfg = of_device_get_match_data(dev);
if (!pll_clk->pll_cfg) {
dev_err(dev, "No OF match data provided\n");
return -EINVAL;
}
ret = devm_clk_hw_register(dev, &pll_clk->hw);
if (ret) {
dev_err(dev, "failed to register %s clock\n", init.name);
return ret;
}
return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
&pll_clk->hw);
}
static int axs10x_pll_clk_remove(struct platform_device *pdev)
{
of_clk_del_provider(pdev->dev.of_node);
return 0;
}
static void __init of_axs10x_pll_clk_setup(struct device_node *node)
{
const char *parent_name;
struct axs10x_pll_clk *pll_clk;
struct clk_init_data init = { };
int ret;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (!pll_clk)
return;
pll_clk->base = of_iomap(node, 0);
if (!pll_clk->base) {
pr_err("failed to map pll div registers\n");
goto err_free_pll_clk;
}
pll_clk->lock = of_iomap(node, 1);
if (!pll_clk->lock) {
pr_err("failed to map pll lock register\n");
goto err_unmap_base;
}
init.name = node->name;
init.ops = &axs10x_pll_ops;
parent_name = of_clk_get_parent_name(node, 0);
init.parent_names = &parent_name;
init.num_parents = parent_name ? 1 : 0;
pll_clk->hw.init = &init;
pll_clk->pll_cfg = arc_pll_cfg;
ret = clk_hw_register(NULL, &pll_clk->hw);
if (ret) {
pr_err("failed to register %s clock\n", node->name);
goto err_unmap_lock;
}
ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
if (ret) {
pr_err("failed to add hw provider for %s clock\n", node->name);
goto err_unregister_clk;
}
return;
err_unregister_clk:
clk_hw_unregister(&pll_clk->hw);
err_unmap_lock:
iounmap(pll_clk->lock);
err_unmap_base:
iounmap(pll_clk->base);
err_free_pll_clk:
kfree(pll_clk);
}
CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
of_axs10x_pll_clk_setup);
static const struct of_device_id axs10x_pll_clk_id[] = {
{ .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
{ }
};
MODULE_DEVICE_TABLE(of, axs10x_pll_clk_id);
static struct platform_driver axs10x_pll_clk_driver = {
.driver = {
.name = "axs10x-pll-clock",
.of_match_table = axs10x_pll_clk_id,
},
.probe = axs10x_pll_clk_probe,
.remove = axs10x_pll_clk_remove,
};
builtin_platform_driver(axs10x_pll_clk_driver);
MODULE_AUTHOR("Vlad Zakharov <vzakhar@synopsys.com>");
MODULE_DESCRIPTION("Synopsys AXS10X SDP Generic PLL Clock Driver");
MODULE_LICENSE("GPL v2");
......@@ -679,8 +679,7 @@ static void __init berlin2_clock_setup(struct device_node *np)
if (!IS_ERR(hws[n]))
continue;
pr_err("%s: Unable to register leaf clock %d\n",
np->full_name, n);
pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
goto bg2_fail;
}
......
......@@ -304,14 +304,14 @@ static void __init berlin2q_clock_setup(struct device_node *np)
gbase = of_iomap(parent_np, 0);
if (!gbase) {
pr_err("%s: Unable to map global base\n", np->full_name);
pr_err("%pOF: Unable to map global base\n", np);
return;
}
/* BG2Q CPU PLL is not part of global registers */
cpupll_base = of_iomap(parent_np, 1);
if (!cpupll_base) {
pr_err("%s: Unable to map cpupll base\n", np->full_name);
pr_err("%pOF: Unable to map cpupll base\n", np);
iounmap(gbase);
return;
}
......@@ -376,8 +376,7 @@ static void __init berlin2q_clock_setup(struct device_node *np)
if (!IS_ERR(hws[n]))
continue;
pr_err("%s: Unable to register leaf clock %d\n",
np->full_name, n);
pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
goto bg2q_fail;
}
......
......@@ -338,8 +338,8 @@ static void __init asm9260_acc_init(struct device_node *np)
if (!IS_ERR(hws[n]))
continue;
pr_err("%s: Unable to register leaf clock %d\n",
np->full_name, n);
pr_err("%pOF: Unable to register leaf clock %d\n",
np, n);
goto fail;
}
......
......@@ -23,8 +23,8 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
"#clock-cells");
if (num_parents == -EINVAL)
pr_err("clk: invalid value of clock-parents property at %s\n",
node->full_name);
pr_err("clk: invalid value of clock-parents property at %pOF\n",
node);
for (index = 0; index < num_parents; index++) {
rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
......@@ -41,8 +41,8 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
pclk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(pclk)) {
if (PTR_ERR(pclk) != -EPROBE_DEFER)
pr_warn("clk: couldn't get parent clock %d for %s\n",
index, node->full_name);
pr_warn("clk: couldn't get parent clock %d for %pOF\n",
index, node);
return PTR_ERR(pclk);
}
......@@ -57,8 +57,8 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EPROBE_DEFER)
pr_warn("clk: couldn't get assigned clock %d for %s\n",
index, node->full_name);
pr_warn("clk: couldn't get assigned clock %d for %pOF\n",
index, node);
rc = PTR_ERR(clk);
goto err;
}
......@@ -102,8 +102,8 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier)
clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EPROBE_DEFER)
pr_warn("clk: couldn't get clock %d for %s\n",
index, node->full_name);
pr_warn("clk: couldn't get clock %d for %pOF\n",
index, node);
return PTR_ERR(clk);
}
......
......@@ -343,6 +343,15 @@ static int cs2000_set_rate(struct clk_hw *hw,
return __cs2000_set_rate(priv, ch, rate, parent_rate);
}
static int cs2000_set_saved_rate(struct cs2000_priv *priv)
{
int ch = 0; /* it uses ch0 only at this point */
return __cs2000_set_rate(priv, ch,
priv->saved_rate,
priv->saved_parent_rate);
}
static int cs2000_enable(struct clk_hw *hw)
{
struct cs2000_priv *priv = hw_to_priv(hw);
......@@ -535,11 +544,8 @@ static int cs2000_probe(struct i2c_client *client,
static int cs2000_resume(struct device *dev)
{
struct cs2000_priv *priv = dev_get_drvdata(dev);
int ch = 0; /* it uses ch0 only at this point */
return __cs2000_set_rate(priv, ch,
priv->saved_rate,
priv->saved_parent_rate);
return cs2000_set_saved_rate(priv);
}
static const struct dev_pm_ops cs2000_pm_ops = {
......
......@@ -385,12 +385,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_divider *divider = to_clk_divider(hw);
unsigned int value;
int value;
unsigned long flags = 0;
u32 val;
value = divider_get_val(rate, parent_rate, divider->table,
divider->width, divider->flags);
if (value < 0)
return value;
if (divider->lock)
spin_lock_irqsave(divider->lock, flags);
......@@ -403,7 +405,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
val = clk_readl(divider->reg);
val &= ~(div_mask(divider->width) << divider->shift);
}
val |= value << divider->shift;
val |= (u32)value << divider->shift;
clk_writel(val, divider->reg);
if (divider->lock)
......
......@@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
return ret;
}
static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate,
unsigned long *m, unsigned long *n)
{
struct clk_fractional_divider *fd = to_clk_fd(hw);
unsigned long scale;
unsigned long m, n;
u64 ret;
if (!rate || rate >= *parent_rate)
return *parent_rate;
/*
* Get rate closer to *parent_rate to guarantee there is no overflow
......@@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
rational_best_approximation(rate, *parent_rate,
GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
&m, &n);
m, n);
}
static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct clk_fractional_divider *fd = to_clk_fd(hw);
unsigned long m, n;
u64 ret;
if (!rate || rate >= *parent_rate)
return *parent_rate;
if (fd->approximation)
fd->approximation(hw, rate, parent_rate, &m, &n);
else
clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
ret = (u64)*parent_rate * m;
do_div(ret, n);
......
......@@ -86,7 +86,7 @@ static void clk_gate_disable(struct clk_hw *hw)
clk_gate_endisable(hw, 0);
}
static int clk_gate_is_enabled(struct clk_hw *hw)
int clk_gate_is_enabled(struct clk_hw *hw)
{
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
......@@ -101,6 +101,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
return reg ? 1 : 0;
}
EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
const struct clk_ops clk_gate_ops = {
.enable = clk_gate_enable,
......
......@@ -37,7 +37,6 @@ static DEFINE_SPINLOCK(gemini_clk_lock);
#define GEMINI_GLOBAL_MISC_CONTROL 0x30
#define PCI_CLK_66MHZ BIT(18)
#define PCI_CLK_OE BIT(17)
#define GEMINI_GLOBAL_CLOCK_CONTROL 0x34
#define PCI_CLKRUN_EN BIT(16)
......@@ -159,9 +158,6 @@ static int gemini_pci_enable(struct clk_hw *hw)
regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
0, PCI_CLKRUN_EN);
regmap_update_bits(pciclk->map,
GEMINI_GLOBAL_MISC_CONTROL,
0, PCI_CLK_OE);
return 0;
}
......@@ -169,9 +165,6 @@ static void gemini_pci_disable(struct clk_hw *hw)
{
struct clk_gemini_pci *pciclk = to_pciclk(hw);
regmap_update_bits(pciclk->map,
GEMINI_GLOBAL_MISC_CONTROL,
PCI_CLK_OE, 0);
regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
PCI_CLKRUN_EN, 0);
}
......
This diff is collapsed.
/*
* Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
* Copyright (C) 2015 Linaro Ltd.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/cpu.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/topology.h>
#include <linux/mailbox_client.h>
#include <linux/platform_device.h>
#include <soc/mb86s7x/scb_mhu.h>
#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
struct mb86s7x_peri_clk {
u32 payload_size;
u32 cntrlr;
u32 domain;
u32 port;
u32 en;
u64 frequency;
} __packed __aligned(4);
struct hack_rate {
unsigned clk_id;
unsigned long rate;
int gated;
};
struct crg_clk {
struct clk_hw hw;
u8 cntrlr, domain, port;
};
static int crg_gate_control(struct clk_hw *hw, int en)
{
struct crg_clk *crgclk = to_crg_clk(hw);
struct mb86s7x_peri_clk cmd;
int ret;
cmd.payload_size = sizeof(cmd);
cmd.cntrlr = crgclk->cntrlr;
cmd.domain = crgclk->domain;
cmd.port = crgclk->port;
cmd.en = en;
/* Port is UngatedCLK */
if (cmd.port == 8)
return en ? 0 : -EINVAL;
pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
__func__, __LINE__, cmd.cntrlr,
cmd.domain, cmd.port, cmd.en);
ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
&cmd, sizeof(cmd));
if (ret < 0) {
pr_err("%s:%d failed!\n", __func__, __LINE__);
return ret;
}
pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
__func__, __LINE__, cmd.cntrlr,
cmd.domain, cmd.port, cmd.en);
/* If the request was rejected */
if (cmd.en != en)
ret = -EINVAL;
else
ret = 0;
return ret;
}
static int crg_port_prepare(struct clk_hw *hw)
{
return crg_gate_control(hw, 1);
}
static void crg_port_unprepare(struct clk_hw *hw)
{
crg_gate_control(hw, 0);
}
static int
crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
{
struct crg_clk *crgclk = to_crg_clk(hw);
struct mb86s7x_peri_clk cmd;
int code, ret;
cmd.payload_size = sizeof(cmd);
cmd.cntrlr = crgclk->cntrlr;
cmd.domain = crgclk->domain;
cmd.port = crgclk->port;
cmd.frequency = *rate;
if (set) {
code = CMD_PERI_CLOCK_RATE_SET_REQ;
pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
__func__, __LINE__, cmd.cntrlr,
cmd.domain, cmd.port, cmd.frequency);
} else {
code = CMD_PERI_CLOCK_RATE_GET_REQ;
pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
__func__, __LINE__, cmd.cntrlr,
cmd.domain, cmd.port);
}
ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
if (ret < 0) {
pr_err("%s:%d failed!\n", __func__, __LINE__);
return ret;
}
if (set)
pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
__func__, __LINE__, cmd.cntrlr,
cmd.domain, cmd.port, cmd.frequency);
else
pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
__func__, __LINE__, cmd.cntrlr,
cmd.domain, cmd.port, cmd.frequency);
*rate = cmd.frequency;
return 0;
}
static unsigned long
crg_port_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
unsigned long rate;
crg_rate_control(hw, 0, &rate);
return rate;
}
static long
crg_port_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *pr)
{
return rate;
}
static int
crg_port_set_rate(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate)
{
return crg_rate_control(hw, 1, &rate);
}
const struct clk_ops crg_port_ops = {
.prepare = crg_port_prepare,
.unprepare = crg_port_unprepare,
.recalc_rate = crg_port_recalc_rate,
.round_rate = crg_port_round_rate,
.set_rate = crg_port_set_rate,
};
struct mb86s70_crg11 {
struct mutex lock; /* protects CLK populating and searching */
};
static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
{
struct mb86s70_crg11 *crg11 = data;
struct clk_init_data init;
u32 cntrlr, domain, port;
struct crg_clk *crgclk;
struct clk *clk;
char clkp[20];
if (clkspec->args_count != 3)
return ERR_PTR(-EINVAL);
cntrlr = clkspec->args[0];
domain = clkspec->args[1];
port = clkspec->args[2];
if (port > 7)
snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
else
snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
mutex_lock(&crg11->lock);
clk = __clk_lookup(clkp);
if (clk) {
mutex_unlock(&crg11->lock);
return clk;
}
crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
if (!crgclk) {
mutex_unlock(&crg11->lock);
return ERR_PTR(-ENOMEM);
}
init.name = clkp;
init.num_parents = 0;
init.ops = &crg_port_ops;
init.flags = 0;
crgclk->hw.init = &init;
crgclk->cntrlr = cntrlr;
crgclk->domain = domain;
crgclk->port = port;
clk = clk_register(NULL, &crgclk->hw);
if (IS_ERR(clk))
pr_err("%s:%d Error!\n", __func__, __LINE__);
else
pr_debug("Registered %s\n", clkp);
clk_register_clkdev(clk, clkp, NULL);
mutex_unlock(&crg11->lock);
return clk;
}
static void __init crg_port_init(struct device_node *node)
{
struct mb86s70_crg11 *crg11;
crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
if (!crg11)
return;
mutex_init(&crg11->lock);
of_clk_add_provider(node, crg11_get, crg11);
}
CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
struct cl_clk {
struct clk_hw hw;
int cluster;
};
struct mb86s7x_cpu_freq {
u32 payload_size;
u32 cluster_class;
u32 cluster_id;
u32 cpu_id;
u64 frequency;
};
static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
{
struct cl_clk *clc = to_clc_clk(hw);
struct mb86s7x_cpu_freq cmd;
int code, ret;
cmd.payload_size = sizeof(cmd);
cmd.cluster_class = 0;
cmd.cluster_id = clc->cluster;
cmd.cpu_id = 0;
cmd.frequency = *rate;
if (get)
code = CMD_CPU_CLOCK_RATE_GET_REQ;
else
code = CMD_CPU_CLOCK_RATE_SET_REQ;
pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
__func__, __LINE__, cmd.cluster_class,
cmd.cluster_id, cmd.cpu_id, cmd.frequency);
ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
if (ret < 0) {
pr_err("%s:%d failed!\n", __func__, __LINE__);
return;
}
pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
__func__, __LINE__, cmd.cluster_class,
cmd.cluster_id, cmd.cpu_id, cmd.frequency);
*rate = cmd.frequency;
}
static unsigned long
clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
{
unsigned long rate;
mhu_cluster_rate(hw, &rate, 1);
return rate;
}
static long
clc_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *unused)
{
return rate;
}
static int
clc_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long unused)
{
unsigned long res = rate;
mhu_cluster_rate(hw, &res, 0);
return (res == rate) ? 0 : -EINVAL;
}
static struct clk_ops clk_clc_ops = {
.recalc_rate = clc_recalc_rate,
.round_rate = clc_round_rate,
.set_rate = clc_set_rate,
};
static struct clk_hw *mb86s7x_clclk_register(struct device *cpu_dev)
{
struct clk_init_data init;
struct cl_clk *clc;
int ret;
clc = kzalloc(sizeof(*clc), GFP_KERNEL);
if (!clc)
return ERR_PTR(-ENOMEM);
clc->hw.init = &init;
clc->cluster = topology_physical_package_id(cpu_dev->id);
init.name = dev_name(cpu_dev);
init.ops = &clk_clc_ops;
init.flags = CLK_GET_RATE_NOCACHE;
init.num_parents = 0;
ret = devm_clk_hw_register(cpu_dev, &clc->hw);
if (ret)
return ERR_PTR(ret);
return &clc->hw;
}
static int mb86s7x_clclk_of_init(void)
{
int cpu, ret = -ENODEV;
struct device_node *np;
struct clk_hw *hw;
np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
if (!np || !of_device_is_available(np))
goto exit;
for_each_possible_cpu(cpu) {
struct device *cpu_dev = get_cpu_device(cpu);
if (!cpu_dev) {
pr_err("failed to get cpu%d device\n", cpu);
continue;
}
hw = mb86s7x_clclk_register(cpu_dev);
if (IS_ERR(hw)) {
pr_err("failed to register cpu%d clock\n", cpu);
continue;
}
if (clk_hw_register_clkdev(hw, NULL, dev_name(cpu_dev))) {
pr_err("failed to register cpu%d clock lookup\n", cpu);
continue;
}
pr_debug("registered clk for %s\n", dev_name(cpu_dev));
}
ret = 0;
platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
exit:
of_node_put(np);
return ret;
}
module_init(mb86s7x_clclk_of_init);
......@@ -18,7 +18,7 @@
static void __init moxart_of_pll_clk_init(struct device_node *node)
{
static void __iomem *base;
void __iomem *base;
struct clk_hw *hw;
struct clk *ref_clk;
unsigned int mul;
......@@ -30,7 +30,7 @@ static void __init moxart_of_pll_clk_init(struct device_node *node)
base = of_iomap(node, 0);
if (!base) {
pr_err("%s: of_iomap failed\n", node->full_name);
pr_err("%pOF: of_iomap failed\n", node);
return;
}
......@@ -39,13 +39,13 @@ static void __init moxart_of_pll_clk_init(struct device_node *node)
ref_clk = of_clk_get(node, 0);
if (IS_ERR(ref_clk)) {
pr_err("%s: of_clk_get failed\n", node->full_name);
pr_err("%pOF: of_clk_get failed\n", node);
return;
}
hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
if (IS_ERR(hw)) {
pr_err("%s: failed to register clock\n", node->full_name);
pr_err("%pOF: failed to register clock\n", node);
return;
}
......@@ -57,7 +57,7 @@ CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
static void __init moxart_of_apb_clk_init(struct device_node *node)
{
static void __iomem *base;
void __iomem *base;
struct clk_hw *hw;
struct clk *pll_clk;
unsigned int div, val;
......@@ -70,7 +70,7 @@ static void __init moxart_of_apb_clk_init(struct device_node *node)
base = of_iomap(node, 0);
if (!base) {
pr_err("%s: of_iomap failed\n", node->full_name);
pr_err("%pOF: of_iomap failed\n", node);
return;
}
......@@ -83,13 +83,13 @@ static void __init moxart_of_apb_clk_init(struct device_node *node)
pll_clk = of_clk_get(node, 0);
if (IS_ERR(pll_clk)) {
pr_err("%s: of_clk_get failed\n", node->full_name);
pr_err("%pOF: of_clk_get failed\n", node);
return;
}
hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
if (IS_ERR(hw)) {
pr_err("%s: failed to register clock\n", node->full_name);
pr_err("%pOF: failed to register clock\n", node);
return;
}
......
......@@ -12,6 +12,7 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/fsl/guts.h>
#include <linux/io.h>
#include <linux/kernel.h>
......@@ -536,6 +537,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
.pll_mask = 0x07,
.flags = CG_PLL_8BIT,
},
{
.compat = "fsl,ls1088a-clockgen",
.cmux_groups = {
&clockgen2_cmux_cga12
},
.cmux_to_group = {
0, 0, -1
},
.pll_mask = 0x07,
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
},
{
.compat = "fsl,ls1012a-clockgen",
.cmux_groups = {
......@@ -1113,6 +1125,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
struct clk *clk;
int ret;
snprintf(pll->div[i].name, sizeof(pll->div[i].name),
"cg-pll%d-div%d", idx, i + 1);
......@@ -1126,6 +1139,11 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
}
pll->div[i].clk = clk;
ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
if (ret != 0)
pr_err("%s: %s: register to lookup table failed %ld\n",
__func__, pll->div[i].name, PTR_ERR(clk));
}
}
......@@ -1348,8 +1366,7 @@ static void __init clockgen_init(struct device_node *np)
}
if (i == ARRAY_SIZE(chipinfo)) {
pr_err("%s: unknown clockgen node %s\n", __func__,
np->full_name);
pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
goto err;
}
clockgen.info = chipinfo[i];
......@@ -1362,8 +1379,8 @@ static void __init clockgen_init(struct device_node *np)
if (guts) {
clockgen.guts = of_iomap(guts, 0);
if (!clockgen.guts) {
pr_err("%s: Couldn't map %s regs\n", __func__,
guts->full_name);
pr_err("%s: Couldn't map %pOF regs\n", __func__,
guts);
}
}
......@@ -1398,6 +1415,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
/* Legacy nodes */
......
......@@ -519,6 +519,11 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
SI5351_CLK_INTEGER_MODE,
(hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
/* Do a pll soft reset on the affected pll */
si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
hwdata->num == 0 ? SI5351_PLL_RESET_A :
SI5351_PLL_RESET_B);
dev_dbg(&hwdata->drvdata->client->dev,
"%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
__func__, clk_hw_get_name(hw),
......@@ -1091,13 +1096,6 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
SI5351_CLK_POWERDOWN, 0);
/*
* Do a pll soft reset on both plls, needed in some cases to get
* all outputs running.
*/
si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
dev_dbg(&hwdata->drvdata->client->dev,
"%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
__func__, clk_hw_get_name(hw), (1 << rdiv),
......
......@@ -1541,8 +1541,8 @@ static void __init stm32f4_rcc_init(struct device_node *np)
base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
if (IS_ERR(clks[idx])) {
pr_err("%s: Unable to register leaf clock %s\n",
np->full_name, gd->name);
pr_err("%pOF: Unable to register leaf clock %s\n",
np, gd->name);
goto fail;
}
}
......
This diff is collapsed.
......@@ -57,6 +57,7 @@
#define VC5_PRIM_SRC_SHDN 0x10
#define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
#define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
#define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
#define VC5_PRIM_SRC_SHDN_SP BIT(1)
#define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
......@@ -122,12 +123,16 @@
/* flags to describe chip features */
/* chip has built-in oscilator */
#define VC5_HAS_INTERNAL_XTAL BIT(0)
/* chip has PFD requency doubler */
#define VC5_HAS_PFD_FREQ_DBL BIT(1)
/* Supported IDT VC5 models. */
enum vc5_model {
IDT_VC5_5P49V5923,
IDT_VC5_5P49V5925,
IDT_VC5_5P49V5933,
IDT_VC5_5P49V5935,
IDT_VC6_5P49V6901,
};
/* Structure to describe features of a particular VC5 model */
......@@ -157,6 +162,8 @@ struct vc5_driver_data {
struct clk *pin_clkin;
unsigned char clk_mux_ins;
struct clk_hw clk_mux;
struct clk_hw clk_mul;
struct clk_hw clk_pfd;
struct vc5_hw_data clk_pll;
struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
struct vc5_hw_data clk_out[VC5_MAX_CLK_OUT_NUM];
......@@ -166,6 +173,14 @@ static const char * const vc5_mux_names[] = {
"mux"
};
static const char * const vc5_dbl_names[] = {
"dbl"
};
static const char * const vc5_pfd_names[] = {
"pfd"
};
static const char * const vc5_pll_names[] = {
"pll"
};
......@@ -254,11 +269,64 @@ static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
}
static unsigned long vc5_mux_recalc_rate(struct clk_hw *hw,
static const struct clk_ops vc5_mux_ops = {
.set_parent = vc5_mux_set_parent,
.get_parent = vc5_mux_get_parent,
};
static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct vc5_driver_data *vc5 =
container_of(hw, struct vc5_driver_data, clk_mux);
container_of(hw, struct vc5_driver_data, clk_mul);
unsigned int premul;
regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
parent_rate *= 2;
return parent_rate;
}
static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
return rate;
else
return -EINVAL;
}
static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct vc5_driver_data *vc5 =
container_of(hw, struct vc5_driver_data, clk_mul);
u32 mask;
if ((parent_rate * 2) == rate)
mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
else
mask = 0;
regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
mask);
return 0;
}
static const struct clk_ops vc5_dbl_ops = {
.recalc_rate = vc5_dbl_recalc_rate,
.round_rate = vc5_dbl_round_rate,
.set_rate = vc5_dbl_set_rate,
};
static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct vc5_driver_data *vc5 =
container_of(hw, struct vc5_driver_data, clk_pfd);
unsigned int prediv, div;
regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
......@@ -276,7 +344,7 @@ static unsigned long vc5_mux_recalc_rate(struct clk_hw *hw,
return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
}
static long vc5_mux_round_rate(struct clk_hw *hw, unsigned long rate,
static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
unsigned long idiv;
......@@ -296,11 +364,11 @@ static long vc5_mux_round_rate(struct clk_hw *hw, unsigned long rate,
return *parent_rate / idiv;
}
static int vc5_mux_set_rate(struct clk_hw *hw, unsigned long rate,
static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct vc5_driver_data *vc5 =
container_of(hw, struct vc5_driver_data, clk_mux);
container_of(hw, struct vc5_driver_data, clk_pfd);
unsigned long idiv;
u8 div;
......@@ -328,12 +396,10 @@ static int vc5_mux_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
static const struct clk_ops vc5_mux_ops = {
.set_parent = vc5_mux_set_parent,
.get_parent = vc5_mux_get_parent,
.recalc_rate = vc5_mux_recalc_rate,
.round_rate = vc5_mux_round_rate,
.set_rate = vc5_mux_set_rate,
static const struct clk_ops vc5_pfd_ops = {
.recalc_rate = vc5_pfd_recalc_rate,
.round_rate = vc5_pfd_round_rate,
.set_rate = vc5_pfd_set_rate,
};
/*
......@@ -426,6 +492,10 @@ static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
(od_frc[2] << 6) | (od_frc[3] >> 2);
/* Avoid division by zero if the output is not configured. */
if (div_int == 0 && div_frc == 0)
return 0;
/* The PLL divider has 12 integer bits and 30 fractional bits */
return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
}
......@@ -503,6 +573,25 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
{
struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
struct vc5_driver_data *vc5 = hwdata->vc5;
const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
VC5_OUT_DIV_CONTROL_SEL_EXT |
VC5_OUT_DIV_CONTROL_EN_FOD;
unsigned int src;
int ret;
/*
* If the input mux is disabled, enable it first and
* select source from matching FOD.
*/
regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
if ((src & mask) == 0) {
src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
ret = regmap_update_bits(vc5->regmap,
VC5_OUT_DIV_CONTROL(hwdata->num),
mask | VC5_OUT_DIV_CONTROL_RESET, src);
if (ret)
return ret;
}
/* Enable the clock buffer */
regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
......@@ -516,7 +605,7 @@ static void vc5_clk_out_unprepare(struct clk_hw *hw)
struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
struct vc5_driver_data *vc5 = hwdata->vc5;
/* Enable the clock buffer */
/* Disable the clock buffer */
regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
}
......@@ -537,6 +626,9 @@ static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
src &= mask;
if (src == 0) /* Input mux set to DISABLED */
return 0;
if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
return 0;
......@@ -595,7 +687,9 @@ static int vc5_map_index_to_output(const enum vc5_model model,
case IDT_VC5_5P49V5933:
return (n == 0) ? 0 : 3;
case IDT_VC5_5P49V5923:
case IDT_VC5_5P49V5925:
case IDT_VC5_5P49V5935:
case IDT_VC6_5P49V6901:
default:
return n;
}
......@@ -672,12 +766,46 @@ static int vc5_probe(struct i2c_client *client,
goto err_clk;
}
if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
/* Register frequency doubler */
memset(&init, 0, sizeof(init));
init.name = vc5_dbl_names[0];
init.ops = &vc5_dbl_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = vc5_mux_names;
init.num_parents = 1;
vc5->clk_mul.init = &init;
ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
if (ret) {
dev_err(&client->dev, "unable to register %s\n",
init.name);
goto err_clk;
}
}
/* Register PFD */
memset(&init, 0, sizeof(init));
init.name = vc5_pfd_names[0];
init.ops = &vc5_pfd_ops;
init.flags = CLK_SET_RATE_PARENT;
if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
init.parent_names = vc5_dbl_names;
else
init.parent_names = vc5_mux_names;
init.num_parents = 1;
vc5->clk_pfd.init = &init;
ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
if (ret) {
dev_err(&client->dev, "unable to register %s\n", init.name);
goto err_clk;
}
/* Register PLL */
memset(&init, 0, sizeof(init));
init.name = vc5_pll_names[0];
init.ops = &vc5_pll_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = vc5_mux_names;
init.parent_names = vc5_pfd_names;
init.num_parents = 1;
vc5->clk_pll.num = 0;
vc5->clk_pll.vc5 = vc5;
......@@ -785,6 +913,13 @@ static const struct vc5_chip_info idt_5p49v5923_info = {
.flags = 0,
};
static const struct vc5_chip_info idt_5p49v5925_info = {
.model = IDT_VC5_5P49V5925,
.clk_fod_cnt = 4,
.clk_out_cnt = 5,
.flags = 0,
};
static const struct vc5_chip_info idt_5p49v5933_info = {
.model = IDT_VC5_5P49V5933,
.clk_fod_cnt = 2,
......@@ -799,18 +934,29 @@ static const struct vc5_chip_info idt_5p49v5935_info = {
.flags = VC5_HAS_INTERNAL_XTAL,
};
static const struct vc5_chip_info idt_5p49v6901_info = {
.model = IDT_VC6_5P49V6901,
.clk_fod_cnt = 4,
.clk_out_cnt = 5,
.flags = VC5_HAS_PFD_FREQ_DBL,
};
static const struct i2c_device_id vc5_id[] = {
{ "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
{ "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
{ "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
{ "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
{ "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
{ }
};
MODULE_DEVICE_TABLE(i2c, vc5_id);
static const struct of_device_id clk_vc5_of_match[] = {
{ .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
{ .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
{ .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
{ .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
{ .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
{ },
};
MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
......
......@@ -192,7 +192,7 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty
reg = of_iomap(np, 0);
if (reg == NULL) {
pr_err("Unable to map CSR register for %s\n", np->full_name);
pr_err("Unable to map CSR register for %pOF\n", np);
return;
}
of_property_read_string(np, "clock-output-names", &clk_name);
......@@ -409,12 +409,12 @@ static void xgene_pmdclk_init(struct device_node *np)
/* Parse the DTS register for resource */
rc = of_address_to_resource(np, 0, &res);
if (rc != 0) {
pr_err("no DTS register for %s\n", np->full_name);
pr_err("no DTS register for %pOF\n", np);
return;
}
csr_reg = of_iomap(np, 0);
if (!csr_reg) {
pr_err("Unable to map resource for %s\n", np->full_name);
pr_err("Unable to map resource for %pOF\n", np);
return;
}
of_property_read_string(np, "clock-output-names", &clk_name);
......@@ -703,16 +703,14 @@ static void __init xgene_devclk_init(struct device_node *np)
rc = of_address_to_resource(np, i, &res);
if (rc != 0) {
if (i == 0) {
pr_err("no DTS register for %s\n",
np->full_name);
pr_err("no DTS register for %pOF\n", np);
return;
}
break;
}
map_res = of_iomap(np, i);
if (map_res == NULL) {
pr_err("Unable to map resource %d for %s\n",
i, np->full_name);
pr_err("Unable to map resource %d for %pOF\n", i, np);
goto err;
}
if (strcmp(res.name, "div-reg") == 0)
......@@ -747,8 +745,7 @@ static void __init xgene_devclk_init(struct device_node *np)
pr_debug("Add %s clock\n", clk_name);
rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
if (rc != 0)
pr_err("%s: could register provider clk %s\n", __func__,
np->full_name);
pr_err("%s: could register provider clk %pOF\n", __func__, np);
return;
......
......@@ -3132,7 +3132,7 @@ int of_clk_add_provider(struct device_node *np,
mutex_lock(&of_clk_mutex);
list_add(&cp->link, &of_clk_providers);
mutex_unlock(&of_clk_mutex);
pr_debug("Added clock from %s\n", np->full_name);
pr_debug("Added clock from %pOF\n", np);
ret = of_clk_set_defaults(np, true);
if (ret < 0)
......@@ -3167,7 +3167,7 @@ int of_clk_add_hw_provider(struct device_node *np,
mutex_lock(&of_clk_mutex);
list_add(&cp->link, &of_clk_providers);
mutex_unlock(&of_clk_mutex);
pr_debug("Added clk_hw provider from %s\n", np->full_name);
pr_debug("Added clk_hw provider from %pOF\n", np);
ret = of_clk_set_defaults(np, true);
if (ret < 0)
......
......@@ -77,8 +77,8 @@ static struct clk *__of_clk_get_by_name(struct device_node *np,
break;
} else if (name && index >= 0) {
if (PTR_ERR(clk) != -EPROBE_DEFER)
pr_err("ERROR: could not get clock %s:%s(%i)\n",
np->full_name, name ? name : "", index);
pr_err("ERROR: could not get clock %pOF:%s(%i)\n",
np, name ? name : "", index);
return clk;
}
......
......@@ -55,9 +55,9 @@ static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
};
static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
{ HI6220_WDT0_PCLK, "wdt0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
{ HI6220_WDT1_PCLK, "wdt1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
{ HI6220_WDT2_PCLK, "wdt2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
{ HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
{ HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
{ HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
......
......@@ -416,10 +416,10 @@ static void __init mx51_clocks_init(struct device_node *np)
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
......
......@@ -71,7 +71,7 @@ static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
static struct clk_div_table clk_enet_ref_table[] = {
static const struct clk_div_table clk_enet_ref_table[] = {
{ .val = 0, .div = 20, },
{ .val = 1, .div = 10, },
{ .val = 2, .div = 5, },
......@@ -79,14 +79,14 @@ static struct clk_div_table clk_enet_ref_table[] = {
{ }
};
static struct clk_div_table post_div_table[] = {
static const struct clk_div_table post_div_table[] = {
{ .val = 2, .div = 1, },
{ .val = 1, .div = 2, },
{ .val = 0, .div = 4, },
{ }
};
static struct clk_div_table video_div_table[] = {
static const struct clk_div_table video_div_table[] = {
{ .val = 0, .div = 1, },
{ .val = 1, .div = 2, },
{ .val = 2, .div = 1, },
......
......@@ -105,7 +105,7 @@ static int const clks_init_on[] __initconst = {
IMX6SX_CLK_EPIT2,
};
static struct clk_div_table clk_enet_ref_table[] = {
static const struct clk_div_table clk_enet_ref_table[] = {
{ .val = 0, .div = 20, },
{ .val = 1, .div = 10, },
{ .val = 2, .div = 5, },
......@@ -113,14 +113,14 @@ static struct clk_div_table clk_enet_ref_table[] = {
{ }
};
static struct clk_div_table post_div_table[] = {
static const struct clk_div_table post_div_table[] = {
{ .val = 2, .div = 1, },
{ .val = 1, .div = 2, },
{ .val = 0, .div = 4, },
{ }
};
static struct clk_div_table video_div_table[] = {
static const struct clk_div_table video_div_table[] = {
{ .val = 0, .div = 1, },
{ .val = 1, .div = 2, },
{ .val = 2, .div = 1, },
......
......@@ -78,7 +78,7 @@ static int const clks_init_on[] __initconst = {
IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
};
static struct clk_div_table clk_enet_ref_table[] = {
static const struct clk_div_table clk_enet_ref_table[] = {
{ .val = 0, .div = 20, },
{ .val = 1, .div = 10, },
{ .val = 2, .div = 5, },
......@@ -86,14 +86,14 @@ static struct clk_div_table clk_enet_ref_table[] = {
{ }
};
static struct clk_div_table post_div_table[] = {
static const struct clk_div_table post_div_table[] = {
{ .val = 2, .div = 1, },
{ .val = 1, .div = 2, },
{ .val = 0, .div = 4, },
{ }
};
static struct clk_div_table video_div_table[] = {
static const struct clk_div_table video_div_table[] = {
{ .val = 0, .div = 1, },
{ .val = 1, .div = 2, },
{ .val = 2, .div = 1, },
......
......@@ -27,7 +27,7 @@ static u32 share_count_sai2;
static u32 share_count_sai3;
static u32 share_count_nand;
static struct clk_div_table test_div_table[] = {
static const struct clk_div_table test_div_table[] = {
{ .val = 3, .div = 1, },
{ .val = 2, .div = 1, },
{ .val = 1, .div = 2, },
......@@ -35,7 +35,7 @@ static struct clk_div_table test_div_table[] = {
{ }
};
static struct clk_div_table post_div_table[] = {
static const struct clk_div_table post_div_table[] = {
{ .val = 3, .div = 4, },
{ .val = 2, .div = 1, },
{ .val = 1, .div = 2, },
......
......@@ -102,7 +102,7 @@ static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_
static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
static struct clk_div_table pll4_audio_div_table[] = {
static const struct clk_div_table pll4_audio_div_table[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 6 },
......
......@@ -27,7 +27,6 @@ static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw)
static u8 clk_cpumux_get_parent(struct clk_hw *hw)
{
struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
int num_parents = clk_hw_get_num_parents(hw);
unsigned int val;
regmap_read(mux->regmap, mux->reg, &val);
......@@ -35,9 +34,6 @@ static u8 clk_cpumux_get_parent(struct clk_hw *hw)
val >>= mux->shift;
val &= mux->mask;
if (val >= num_parents)
return -EINVAL;
return val;
}
......@@ -98,7 +94,7 @@ int __init mtk_clk_register_cpumuxes(struct device_node *node,
regmap = syscon_node_to_regmap(node);
if (IS_ERR(regmap)) {
pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
pr_err("Cannot find regmap for %pOF: %ld\n", node,
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
......
......@@ -114,7 +114,7 @@ int mtk_clk_register_gates(struct device_node *node,
regmap = syscon_node_to_regmap(node);
if (IS_ERR(regmap)) {
pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
pr_err("Cannot find regmap for %pOF: %ld\n", node,
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
......
......@@ -72,7 +72,7 @@ void mtk_register_reset_controller(struct device_node *np,
regmap = syscon_node_to_regmap(np);
if (IS_ERR(regmap)) {
pr_err("Cannot find regmap for %s: %ld\n", np->full_name,
pr_err("Cannot find regmap for %pOF: %ld\n", np,
PTR_ERR(regmap));
return;
}
......
......@@ -6,6 +6,7 @@ config COMMON_CLK_AMLOGIC
config COMMON_CLK_MESON8B
bool
depends on COMMON_CLK_AMLOGIC
select RESET_CONTROLLER
help
Support for the clock controller on AmLogic S802 (Meson8),
S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
......
......@@ -4,4 +4,4 @@
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/clk-provider.h>
#include <linux/bitfield.h>
#include <linux/regmap.h>
#include "gxbb-aoclk.h"
/*
* The AO Domain embeds a dual/divider to generate a more precise
* 32,768KHz clock for low-power suspend mode and CEC.
* ______ ______
* | | | |
* ______ | Div1 |-| Cnt1 | ______
* | | /|______| |______|\ | |
* Xtal-->| Gate |---| ______ ______ X-X--| Gate |-->
* |______| | \| | | |/ | |______|
* | | Div2 |-| Cnt2 | |
* | |______| |______| |
* |_______________________|
*
* The dividing can be switched to single or dual, with a counter
* for each divider to set when the switching is done.
* The entire dividing mechanism can be also bypassed.
*/
#define CLK_CNTL0_N1_MASK GENMASK(11, 0)
#define CLK_CNTL0_N2_MASK GENMASK(23, 12)
#define CLK_CNTL0_DUALDIV_EN BIT(28)
#define CLK_CNTL0_OUT_GATE_EN BIT(30)
#define CLK_CNTL0_IN_GATE_EN BIT(31)
#define CLK_CNTL1_M1_MASK GENMASK(11, 0)
#define CLK_CNTL1_M2_MASK GENMASK(23, 12)
#define CLK_CNTL1_BYPASS_EN BIT(24)
#define CLK_CNTL1_SELECT_OSC BIT(27)
#define PWR_CNTL_ALT_32K_SEL GENMASK(13, 10)
struct cec_32k_freq_table {
unsigned long parent_rate;
unsigned long target_rate;
bool dualdiv;
unsigned int n1;
unsigned int n2;
unsigned int m1;
unsigned int m2;
};
static const struct cec_32k_freq_table aoclk_cec_32k_table[] = {
[0] = {
.parent_rate = 24000000,
.target_rate = 32768,
.dualdiv = true,
.n1 = 733,
.n2 = 732,
.m1 = 8,
.m2 = 11,
},
};
/*
* If CLK_CNTL0_DUALDIV_EN == 0
* - will use N1 divider only
* If CLK_CNTL0_DUALDIV_EN == 1
* - hold M1 cycles of N1 divider then changes to N2
* - hold M2 cycles of N2 divider then changes to N1
* Then we can get more accurate division.
*/
static unsigned long aoclk_cec_32k_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
unsigned long n1;
u32 reg0, reg1;
regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, &reg0);
regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, &reg1);
if (reg1 & CLK_CNTL1_BYPASS_EN)
return parent_rate;
if (reg0 & CLK_CNTL0_DUALDIV_EN) {
unsigned long n2, m1, m2, f1, f2, p1, p2;
n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
n2 = FIELD_GET(CLK_CNTL0_N2_MASK, reg0) + 1;
m1 = FIELD_GET(CLK_CNTL1_M1_MASK, reg1) + 1;
m2 = FIELD_GET(CLK_CNTL1_M2_MASK, reg1) + 1;
f1 = DIV_ROUND_CLOSEST(parent_rate, n1);
f2 = DIV_ROUND_CLOSEST(parent_rate, n2);
p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2));
p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2));
return DIV_ROUND_UP(100000000, p1 + p2);
}
n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
return DIV_ROUND_CLOSEST(parent_rate, n1);
}
static const struct cec_32k_freq_table *find_cec_32k_freq(unsigned long rate,
unsigned long prate)
{
int i;
for (i = 0 ; i < ARRAY_SIZE(aoclk_cec_32k_table) ; ++i)
if (aoclk_cec_32k_table[i].parent_rate == prate &&
aoclk_cec_32k_table[i].target_rate == rate)
return &aoclk_cec_32k_table[i];
return NULL;
}
static long aoclk_cec_32k_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
*prate);
/* If invalid return first one */
if (!freq)
return aoclk_cec_32k_table[0].target_rate;
return freq->target_rate;
}
/*
* From the Amlogic init procedure, the IN and OUT gates needs to be handled
* in the init procedure to avoid any glitches.
*/
static int aoclk_cec_32k_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
parent_rate);
struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
u32 reg = 0;
if (!freq)
return -EINVAL;
/* Disable clock */
regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
CLK_CNTL0_IN_GATE_EN | CLK_CNTL0_OUT_GATE_EN, 0);
reg = FIELD_PREP(CLK_CNTL0_N1_MASK, freq->n1 - 1);
if (freq->dualdiv)
reg |= CLK_CNTL0_DUALDIV_EN |
FIELD_PREP(CLK_CNTL0_N2_MASK, freq->n2 - 1);
regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, reg);
reg = FIELD_PREP(CLK_CNTL1_M1_MASK, freq->m1 - 1);
if (freq->dualdiv)
reg |= FIELD_PREP(CLK_CNTL1_M2_MASK, freq->m2 - 1);
regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, reg);
/* Enable clock */
regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
CLK_CNTL0_IN_GATE_EN, CLK_CNTL0_IN_GATE_EN);
udelay(200);
regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
CLK_CNTL0_OUT_GATE_EN, CLK_CNTL0_OUT_GATE_EN);
regmap_update_bits(cec_32k->regmap, AO_CRT_CLK_CNTL1,
CLK_CNTL1_SELECT_OSC, CLK_CNTL1_SELECT_OSC);
/* Select 32k from XTAL */
regmap_update_bits(cec_32k->regmap,
AO_RTI_PWR_CNTL_REG0,
PWR_CNTL_ALT_32K_SEL,
FIELD_PREP(PWR_CNTL_ALT_32K_SEL, 4));
return 0;
}
const struct clk_ops meson_aoclk_cec_32k_ops = {
.recalc_rate = aoclk_cec_32k_recalc_rate,
.round_rate = aoclk_cec_32k_round_rate,
.set_rate = aoclk_cec_32k_set_rate,
};
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/clk-provider.h>
#include <linux/bitfield.h>
#include <linux/regmap.h>
#include "gxbb-aoclk.h"
static int aoclk_gate_regmap_enable(struct clk_hw *hw)
{
struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
return regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0,
BIT(gate->bit_idx), BIT(gate->bit_idx));
}
static void aoclk_gate_regmap_disable(struct clk_hw *hw)
{
struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0,
BIT(gate->bit_idx), 0);
}
static int aoclk_gate_regmap_is_enabled(struct clk_hw *hw)
{
struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
unsigned int val;
int ret;
ret = regmap_read(gate->regmap, AO_RTI_GEN_CNTL_REG0, &val);
if (ret)
return ret;
return (val & BIT(gate->bit_idx)) != 0;
}
const struct clk_ops meson_aoclk_gate_regmap_ops = {
.enable = aoclk_gate_regmap_enable,
.disable = aoclk_gate_regmap_disable,
.is_enabled = aoclk_gate_regmap_is_enabled,
};
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......@@ -37,6 +37,9 @@
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
......@@ -68,7 +71,11 @@
#define CLK_NR_CLKS 96
/* include the CLKIDs that have been made part of the stable DT binding */
/*
* include the CLKID and RESETID that have
* been made part of the stable DT binding
*/
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#endif /* __MESON8B_H */
......@@ -9,7 +9,7 @@
void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
int nr_clks)
{
static struct clk **clk_table;
struct clk **clk_table;
clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
if (!clk_table)
......
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