Commit f67fd9a6 authored by Takeshi Kihara's avatar Takeshi Kihara Committed by Greg Kroah-Hartman

clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC

[ Upstream commit b9df2ea2 ]

The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:

    Channel        R-Car H3    R-Car M3-W    R-Car M3-N    R-Car E3
    ---------------------------------------------------------------
    Audio-DMAC0    S1D2        S1D2          S1D2          S1D2
    Audio-DMAC1    S1D2        S1D2          S1D2          -

As a result, change the parent clocks of the Audio-DMAC{0,1} module
clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the
parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2.

NOTE: This information will be reflected in a future revision of the
      R-Car Gen3 Hardware Manual.
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car D3, RZ/G2M, and RZ/G2E]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 36478bcf
...@@ -143,8 +143,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { ...@@ -143,8 +143,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("rwdt", 402, R8A774A1_CLK_R), DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP), DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3), DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3), DEF_MOD("audmac1", 501, R8A774A1_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3), DEF_MOD("audmac0", 502, R8A774A1_CLK_S1D2),
DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1), DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1), DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1), DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
......
...@@ -157,7 +157,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { ...@@ -157,7 +157,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP), DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3), DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A774C0_CLK_S3D4), DEF_MOD("audmac0", 502, R8A774C0_CLK_S1D2),
DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C), DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C), DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C), DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
......
...@@ -153,8 +153,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { ...@@ -153,8 +153,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("rwdt", 402, R8A7795_CLK_R), DEF_MOD("rwdt", 402, R8A7795_CLK_R),
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3), DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
......
...@@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { ...@@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("rwdt", 402, R8A7796_CLK_R), DEF_MOD("rwdt", 402, R8A7796_CLK_R),
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3), DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7796_CLK_S3D2), DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
......
...@@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { ...@@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("intc-ex", 407, R8A77965_CLK_CP), DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3), DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3), DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3), DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
DEF_MOD("drif7", 508, R8A77965_CLK_S3D2), DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
DEF_MOD("drif6", 509, R8A77965_CLK_S3D2), DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
DEF_MOD("drif5", 510, R8A77965_CLK_S3D2), DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
......
...@@ -152,7 +152,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { ...@@ -152,7 +152,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("intc-ex", 407, R8A77990_CLK_CP), DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3), DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4), DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
DEF_MOD("drif7", 508, R8A77990_CLK_S3D2), DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
DEF_MOD("drif6", 509, R8A77990_CLK_S3D2), DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
DEF_MOD("drif5", 510, R8A77990_CLK_S3D2), DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
......
...@@ -133,7 +133,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { ...@@ -133,7 +133,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
DEF_MOD("rwdt", 402, R8A77995_CLK_R), DEF_MOD("rwdt", 402, R8A77995_CLK_R),
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2), DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1), DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
DEF_MOD("thermal", 522, R8A77995_CLK_CP), DEF_MOD("thermal", 522, R8A77995_CLK_CP),
......
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